Interferon c482bafdaf There is code in the register allocator to restrict register allocation to the ... first 16 registers in RISC-V RVE and RVEC modes. However, there was still code in tcpuparamanager.create_paraloc_info_intern that allowed the allocation of up to register X17 in RVE and RVEC modes. Modified this function to take the processor mode into account and restrict it to X0..X15 in RVE and RVEC modes. Also put conditional code in setjump.inc assembler code to only set the first 16 registers in RVE and RVEC modes. The entire embedded-riscv32 RTL can now compile successfuly in RVEC mode.		2023-08-26 22:12:00 +02:00
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CH32VxBootstrap.pp	There is code in the register allocator to restrict register allocation to the	2023-08-26 22:12:00 +02:00
fe310g000.pp	Added generic WCH32Vx RISC-V processor types using memory size suffixes	2023-08-26 22:12:00 +02:00
fe310g002.pp	Added generic WCH32Vx RISC-V processor types using memory size suffixes	2023-08-26 22:12:00 +02:00
gd32vf103xx.pp	Added generic WCH32Vx RISC-V processor types using memory size suffixes	2023-08-26 22:12:00 +02:00
riscv32_start.inc	There is code in the register allocator to restrict register allocation to the	2023-08-26 22:12:00 +02:00