sergei 534ecbda9f * SPARC: r26561 caused a_op_const_reg_reg used for zero-extending 8-bit values to be optimized away. Fixed by replacing it with an explicit instruction. ... git-svn-id: trunk@26566 -		2014-01-22 21:37:37 +00:00
..
aasmcpu.pas
aoptcpu.pas	+ SPARC: initial peephole optimizer.	2014-01-21 14:22:59 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* SPARC: r26561 caused a_op_const_reg_reg used for zero-extending 8-bit values to be optimized away. Fixed by replacing it with an explicit instruction.	2014-01-22 21:37:37 +00:00
cpubase.pas	* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.	2013-12-27 06:45:49 +00:00
cpuelf.pas
cpugas.pas	Handle asmextraopt in powerpc, mips and sparc assemblers	2014-01-21 00:19:17 +00:00
cpuinfo.pas
cpunode.pas
cpupara.pas	* SPARC: properly justify parameters on stack with size less than 4, fixes failure on tests/cg/tcalext5.pp	2013-12-28 09:23:10 +00:00
cpupi.pas	* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.	2013-12-27 19:53:38 +00:00
cputarg.pas
hlcgcpu.pas
itcpugas.pas
ncpuadd.pas	* SPARC: reworked 64-bit comparisons so their result is always in flags. Comparisons are emitted as subtractions, sides are optionally swapped to avoid using Z flag (since it is not set correctly in multi-word subtraction). This generates significantly shorter code: when both sides are in registers it is just 3 instructions for equal/unequal and 2 instructions otherwise.	2014-01-12 15:11:47 +00:00
ncpucall.pas
ncpucnv.pas	* SPARC: convert from int64/qword to float using genmath helpers. Removes dependency on softfloat code.	2013-12-22 14:02:34 +00:00
ncpuinln.pas
ncpumat.pas	* SPARC: emit "x shl 1" as "x+x", it yields shorter code.	2014-01-21 13:50:35 +00:00
ncpuset.pas	+ SPARC: generate position-independent case jump tables, as specified by ABI.	2014-01-15 15:31:53 +00:00
opcode.inc	+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.	2013-12-21 16:27:24 +00:00
racpu.pas
racpugas.pas	* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.	2013-12-27 06:45:49 +00:00
rgcpu.pas	+ SPARC: implemented register spill replacement.	2014-01-03 08:14:43 +00:00
rspcon.inc
rspdwrf.inc
rspnor.inc
rspnum.inc
rsprni.inc
rspsri.inc
rspstab.inc
rspstd.inc
rspsup.inc
spreg.dat
strinst.inc	+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.	2013-12-21 16:27:24 +00:00