fpc/compiler/x86_64
Jonas Maebe f36e5411af * split cpu64bit compiler define into
a) cpu64bitaddr, which means that we are generating a compiler which
       will generate code for targets with a 64 bit address space/abi
    b) cpu64bitalu, which means that we are generating a compiler which
       will generate code for a cpu with support for 64 bit integer
       operations (possibly running in a 32 bit address space, depending
       on the cpu64bitaddr define)
   All cpus which had cpu64bit set now have both the above defines set,
   and none of the 32 bit cpus have cpu64bitalu set (and none will
   compile with it currently)
  + pint and puint types, similar to aint/aword (not pword because that
    that conflicts with pword=^word)
  * several changes from aint/aword to pint/pword
  * some changes of tcgsize2size[OS_INT] to sizeof(pint)

git-svn-id: trunk@10320 -
2008-02-13 20:44:00 +00:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpud.pas
cgcpu.pas - removed {$ifndef cpu64bit} code 2008-02-10 17:05:27 +00:00
cpubase.inc + default code now preserves mm registers 2007-10-27 12:02:28 +00:00
cpuinfo.pas * fixed assembling of fisttp of sse3 instruction set 2007-10-27 20:50:46 +00:00
cpunode.pas
cpupara.pas * split cpu64bit compiler define into 2008-02-13 20:44:00 +00:00
cpupi.pas * Also execute setfirsttemp on non-Windows platforms. Fixes -O2 cycle on Linux. 2007-06-29 17:46:27 +00:00
cputarg.pas
nx64add.pas * fixed location.size for length node and x86_64 mul node 2007-12-15 19:27:24 +00:00
nx64cal.pas
nx64cnv.pas * also use sse2 instructions to convert int to real on i386 2007-12-09 18:10:23 +00:00
nx64inl.pas
nx64mat.pas * fixed location.size for divmodn (in particular the sign) 2007-12-09 18:06:44 +00:00
r8664ari.inc
r8664att.inc
r8664con.inc
r8664dwrf.inc
r8664int.inc
r8664iri.inc
r8664nor.inc
r8664num.inc
r8664op.inc
r8664ot.inc
r8664rni.inc
r8664sri.inc
r8664stab.inc
r8664std.inc
rax64att.pas * enabled operand size checking (don't know why it was disabled, 2007-12-15 22:30:23 +00:00
rax64int.pas
rgcpu.pas
x8664ats.inc * added missing size suffixes for several sse2 opcodes 2007-11-10 19:57:01 +00:00
x8664att.inc + some sse4 instructions supported, resolves #9046 2007-06-09 19:45:06 +00:00
x8664int.inc + some sse4 instructions supported, resolves #9046 2007-06-09 19:45:06 +00:00
x8664nop.inc * Jcc reads the flags, this was not in the dat yet, resolves #9278 2007-07-22 16:40:44 +00:00
x8664op.inc + some sse4 instructions supported, resolves #9046 2007-06-09 19:45:06 +00:00
x8664pro.inc * Jcc reads the flags, this was not in the dat yet, resolves #9278 2007-07-22 16:40:44 +00:00
x8664tab.inc * fixed more rex placements 2007-11-02 21:30:43 +00:00