sergei e7f6b06969 + MIPS internal linker: support TLS IE/LE and GPREL32 relocations, is now able to link tw14265. ... git-svn-id: trunk@25181 -		2013-07-29 09:30:40 +00:00
..
aasmcpu.pas	+ MIPS: Use INS and EXT instructions for bit manipulations when target CPU type is set to mips32r2.	2013-07-02 14:21:29 +00:00
aoptcpu.pas	+ MIPS: started the peephole optimizer.	2013-07-20 13:44:21 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* MIPS: set pi_do_call flag for assembler procedures with stackframes, so in PIC mode it further receives pi_needs_got in PIC mode and allocates the GP save temp.	2013-07-20 13:42:41 +00:00
cpubase.pas	+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.	2013-07-19 14:06:47 +00:00
cpuelf.pas	+ MIPS internal linker: support TLS IE/LE and GPREL32 relocations, is now able to link tw14265.	2013-07-29 09:30:40 +00:00
cpugas.pas	* MIPS: 3-operand forms of DIV and DIVU are not macros if first operand is $zero.	2013-06-20 13:14:38 +00:00
cpuinfo.pas	* Fixed label optimizer to work with MIPS, and enabled level 1 optimization for MIPS targets.	2013-07-03 14:40:24 +00:00
cpunode.pas
cpupara.pas	* MIPS: floating point parameters on stack should be loaded to/from FPU registers directly, without using temp.	2013-07-17 11:00:46 +00:00
cpupi.pas	* MIPS: handle get_frame internally, so it sets pi_needs_stackframe flag on current procedure. This makes possible not to force pi_needs_stackframe on every procedure and thus omit saving/restoring $fp register when it is not necessary.	2013-07-24 15:25:12 +00:00
cputarg.pas
hlcgcpu.pas	+ MIPS: Use INS and EXT instructions for bit manipulations when target CPU type is set to mips32r2.	2013-07-02 14:21:29 +00:00
itcpugas.pas
mipsreg.dat
ncpuadd.pas	+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.	2013-07-19 14:06:47 +00:00
ncpucall.pas
ncpucnv.pas	+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.	2013-07-19 14:06:47 +00:00
ncpuinln.pas	* MIPS: handle get_frame internally, so it sets pi_needs_stackframe flag on current procedure. This makes possible not to force pi_needs_stackframe on every procedure and thus omit saving/restoring $fp register when it is not necessary.	2013-07-24 15:25:12 +00:00
ncpuld.pas
ncpumat.pas	+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.	2013-07-19 14:06:47 +00:00
ncpuset.pas	* MIPS case node: simplified code a bit.	2013-06-15 12:36:21 +00:00
opcode.inc	- MIPS: removed opcodes that are not in any known documentation.	2013-07-01 06:09:53 +00:00
racpugas.pas
rgcpu.pas
rmipscon.inc
rmipsdwf.inc
rmipsgas.inc
rmipsgri.inc
rmipsgss.inc
rmipsnor.inc
rmipsnum.inc
rmipsrni.inc
rmipssri.inc
rmipssta.inc
rmipsstd.inc
rmipssup.inc
strinst.inc	- MIPS: removed opcodes that are not in any known documentation.	2013-07-01 06:09:53 +00:00