fpc/compiler/mips
Jonas Maebe 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint,
so it also works for 32 bit targets and a high level code generator
    (where aint is still 32 bit, but 64 bit operations are not decomposed)

git-svn-id: trunk@41441 -
2019-02-24 19:58:37 +00:00
..
aasmcpu.pas * MIPS: reworked and fixed procedure fixup_jmps: 2016-02-12 13:53:04 +00:00
aoptcpu.pas * MIPS: fixed TCpuAsmOptimizer.InstructionLoadsFromReg, it now correctly considers instructions that read their first operand. 2017-04-23 15:26:17 +00:00
aoptcpub.pas - get rid of MaxOps, it is redundant with max_operands 2018-11-02 21:32:29 +00:00
aoptcpud.pas * more MIPS code of David Zhang integrated 2009-11-20 14:46:45 +00:00
cgcpu.pas * removed temppos field again from parameter locations: they're not allocated 2018-04-27 19:18:55 +00:00
cpubase.pas Fix for bug report #34380 2018-10-18 20:21:54 +00:00
cpuelf.pas * MIPS: some progress with linker: 2016-03-13 17:13:23 +00:00
cpugas.pas * restructured the the TExternalAssembler constructors so that the 2016-11-09 19:51:20 +00:00
cpuinfo.pas - removed unused constants 2017-03-26 13:06:34 +00:00
cpunode.pas * automatically generate necessary indirect symbols when a new assembler 2016-07-20 20:53:03 +00:00
cpupara.pas * keep track of whether a routine has a C-style variadic parameter in the 2019-02-23 15:42:45 +00:00
cpupi.pas * renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can 2016-12-16 22:41:21 +00:00
cputarg.pas * partially merged the mips-embedded branch of Michael Ring: 2014-03-19 21:25:38 +00:00
hlcgcpu.pas * keep track of the temp position separately from the offset in references, 2018-04-22 17:03:16 +00:00
itcpugas.pas * Removed unused vars for mipsel compiler. 2015-09-17 15:46:30 +00:00
mipsreg.dat Fix stabs number for FPU register, which start at 38 instead of 32 2016-11-06 18:01:08 +00:00
ncpuadd.pas * Removed unused vars for mipsel compiler. 2015-09-17 15:46:30 +00:00
ncpucall.pas * use pocalls_cdecl and cstylearrayofconst more consistently instead of 2017-02-25 11:46:35 +00:00
ncpucnv.pas + added volatility information to all memory references 2016-11-27 18:17:37 +00:00
ncpuinln.pas * completed thlcgobj.location_force_fpureg(), use it everywhere and removed 2014-03-10 09:01:05 +00:00
ncpuld.pas - Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels. 2013-06-02 10:49:17 +00:00
ncpumat.pas * synchronised with r28168 of trunk 2014-07-05 21:30:28 +00:00
ncpuset.pas * let all the case code generation work with tconstexprint instead of aint, 2019-02-24 19:58:37 +00:00
opcode.inc + MIPS: added movn and movz instructions. 2014-06-19 22:44:17 +00:00
racpugas.pas * factored out check to determine whether a variable can be subscripted in 2018-01-01 14:29:21 +00:00
rgcpu.pas * keep track of the temp position separately from the offset in references, 2018-04-22 17:03:16 +00:00
rmipscon.inc * MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names. 2014-06-22 22:01:44 +00:00
rmipsdwf.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipsgas.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipsgri.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipsgss.inc + basic mips stuff 2005-02-13 18:56:44 +00:00
rmipsnor.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipsnum.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipsrni.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipssri.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipssta.inc Regenerated after change in mipsreg.dat 2016-11-06 18:01:52 +00:00
rmipsstd.inc * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 2014-06-17 23:15:34 +00:00
rmipssup.inc * MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names. 2014-06-22 22:01:44 +00:00
strinst.inc + MIPS: added movn and movz instructions. 2014-06-19 22:44:17 +00:00
symcpu.pas o fixes handling of iso i/o parameters/program parameters: 2015-05-01 20:58:31 +00:00