Jonas Maebe 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint, ... so it also works for 32 bit targets and a high level code generator (where aint is still 32 bit, but 64 bit operations are not decomposed) git-svn-id: trunk@41441 -		2019-02-24 19:58:37 +00:00
..
aoptcpu.pas	* factored out OptPass1FLD, used bx x86-64 now as well	2019-01-24 20:10:29 +00:00
aoptcpub.pas	- get rid of MaxOps, it is redundant with max_operands	2018-11-02 21:32:29 +00:00
aoptcpud.pas
cgcpu.pas	* forgotten part of r39750	2018-09-13 20:20:40 +00:00
cpubase.inc	* replaced the saved_XXX_registers arrays with virtual methods inside	2018-04-19 21:22:16 +00:00
cpuelf.pas	haiku-x86_64: add target to the compiler and ppudump, enable it in fpmake and fpcmake	2019-01-04 02:16:24 +00:00
cpuinfo.pas	+ implementation of the vectorcall calling convention by J. Gareth Moreton	2018-02-11 17:50:37 +00:00
cpunode.pas	+ tls support for x86_64-linux (not yet enabled by default)	2019-01-27 09:37:25 +00:00
cpupara.pas	* keep track of whether a routine has a C-style variadic parameter in the	2019-02-23 15:42:45 +00:00
cpupi.pas	* forgotten part of r39750	2018-09-13 20:20:40 +00:00
cputarg.pas	haiku-x86_64: add target to the compiler and ppudump, enable it in fpmake and fpcmake	2019-01-04 02:16:24 +00:00
hlcgcpu.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
nx64add.pas	* removed unused units	2017-05-09 19:53:14 +00:00
nx64cal.pas	* removed unused units	2017-05-09 19:53:14 +00:00
nx64cnv.pas	* removed unused units	2017-05-09 19:53:14 +00:00
nx64flw.pas	* moved around/replaced the following procedures to stop nflw from depending	2019-01-05 16:26:33 +00:00
nx64inl.pas
nx64mat.pas	+ support mmx shifting	2018-02-27 21:40:12 +00:00
nx64set.pas	* let all the case code generation work with tconstexprint instead of aint,	2019-02-24 19:58:37 +00:00
r8664ari.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664att.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664con.inc	* fix flag subregs after r38206	2018-03-11 20:30:11 +00:00
r8664dwrf.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664int.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664iri.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664nasm.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664nor.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664num.inc	* fix flag subregs after r38206	2018-03-11 20:30:11 +00:00
r8664ot.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664rni.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664sri.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664stab.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r8664std.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
rax64att.pas	* fix .seh_savereg: the offset is checked with a bitmask, not a divisor, so use "and", not "mod"	2018-10-07 12:25:09 +00:00
rax64int.pas	+ (slightly) patch by Emelyanov Roman to add support of SEH directive in FPC internal assembler with INTEL syntax, resolves #29894	2018-02-24 16:14:08 +00:00
rgcpu.pas
symcpu.pas	* when creating wrappers, add a prefix to parameter names to prevent them	2018-12-24 22:10:06 +00:00
win64unw.pas
x8664ats.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00
x8664att.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00
x8664int.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00
x8664nop.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00
x8664op.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00
x8664pro.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00
x8664tab.inc	+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799	2019-01-20 18:50:12 +00:00