florian b733e21fd1 + more AArch64 extensions		2021-11-20 20:47:47 +01:00
..
a64att.inc	+ some opcodes added	2021-10-30 20:21:59 +02:00
a64atts.inc	+ some opcodes added	2021-10-30 20:21:59 +02:00
a64ins.dat	+ some opcodes added	2021-10-30 20:21:59 +02:00
a64nop.inc
a64op.inc	+ some opcodes added	2021-10-30 20:21:59 +02:00
a64reg.dat	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
a64tab.inc	* corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by	2015-05-14 14:42:12 +00:00
aasmcpu.pas	+ Aaarch64: support adr instructions with local labels in the assembler reader	2021-11-19 22:37:47 +01:00
agcpugas.pas	+ more AArch64 extensions	2021-11-20 20:47:47 +01:00
aoptcpu.pas	* AArch64: TCpuAsmOptimizer.RegLoadedWithNewValue: check if p.ops=0	2021-11-01 11:46:19 +01:00
aoptcpub.pas	* fix case completeness and unreachable code warnings in compiler that would	2019-05-12 14:29:03 +00:00
aoptcpud.pas
cgcpu.pas	* avoid to create a stack frame on aarch64 if possible	2021-11-02 22:23:24 +01:00
cpubase.pas	* tcgsizep2size now supports all tcgsize values	2021-11-06 21:16:07 +01:00
cpuinfo.pas	+ more AArch64 extensions	2021-11-20 20:47:47 +01:00
cpunode.pas	+ implement compiler support for SEH on Win64	2020-04-21 06:06:05 +00:00
cpupara.pas	* cleanup of VER3_0 defines	2021-11-17 22:19:57 +01:00
cpupi.pas	+ implement compiler support for SEH on Win64	2020-04-21 06:06:05 +00:00
cputarg.pas	+ FreeBSD/AArch64 support (patch by Mikaël Urankar, mantis #38441)	2021-04-10 07:57:28 +00:00
hlcgcpu.pas	* AArch64: fix storing a 32 bit value in the lower 32 bits of a 64 bit	2021-04-19 20:52:12 +00:00
itcpugas.pas	+ ARM64 GAS instruction table unit	2012-11-01 20:09:47 +00:00
ncpuadd.pas	+ support for software floating point exception handling on AArch64 (-CE)	2019-09-01 17:26:11 +00:00
ncpucnv.pas	* Removed unused local vars.	2018-11-02 18:44:29 +00:00
ncpucon.pas	* avoid that -0.0 is handled by the eor optimization	2019-09-04 20:45:24 +00:00
ncpuflw.pas	* patch by Marģers to unify internal error numbers, resolves #37888	2020-10-13 19:59:01 +00:00
ncpuinl.pas	+ Aarch64: directly inline code for frac(...)	2021-04-25 09:26:47 +00:00
ncpumat.pas	Avoid range/overflow error after commit #49290	2021-04-30 09:55:11 +00:00
ncpumem.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
ncpuset.pas	* generate jump tables into the same section as the code as otherwise we'll get bogus relocations (in case of clang.exe) or a future support for armasm64.exe will reject the relative symbols outright	2020-04-21 06:06:36 +00:00
ra64con.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64dwa.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64nor.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64num.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64rni.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64sri.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64sta.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64std.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
ra64sup.inc	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
racpu.pas	* AArch64: added SIMD instructions (only plain ARMv8-A for now)	2020-10-15 20:29:36 +00:00
racpugas.pas	+ Aarch64: read register sets with ranges properly	2021-11-07 20:02:29 +01:00
rgcpu.pas	* AArch64: fix spilling integer registers to stack offsets that cannot be	2021-04-14 20:56:32 +00:00
symcpu.pas	o fixes handling of iso i/o parameters/program parameters:	2015-05-01 20:58:31 +00:00
tripletcpu.pas	* mark all external assemblers using an LLVM tool using af_llvm	2020-07-19 14:30:35 +00:00