masta ff95d42216 Fix ShiftShift2Shift 1 ARM-peephole optimizer ... The previous code deleted the newly inserted instruction instead of the existing one, which obviously broke code. Assembly: mov r0, r0, lsr #23 mov r0, r0, lsr #23 transformed into: mov r0, r0, lsr #23 expected was: mov r0, #0 The problem only shows up in the very unlikely case of two LSR/ASR or two LSL following on each other and having a total shift of more than 31 bits. This fixes test/opt/tarmshift.pp I've also removed the {%norun} directive from tarmshift.pp as this test does only make sense when it also runs. git-svn-id: trunk@25374 -		2013-08-26 17:41:54 +00:00
..
aasmcpu.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
agarmgas.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
aoptcpu.pas	Fix ShiftShift2Shift 1 ARM-peephole optimizer	2013-08-26 17:41:54 +00:00
aoptcpub.pas	* set MaxOps to 4 for the optimizer because fpc generates now mla instructions	2012-08-17 12:38:59 +00:00
aoptcpuc.pas
aoptcpud.pas
armatt.inc	+ SVC instruction	2013-03-24 20:22:06 +00:00
armatts.inc	+ SVC instruction	2013-03-24 20:22:06 +00:00
armins.dat	+ SVC instruction	2013-03-24 20:22:06 +00:00
armnop.inc	Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)	2012-10-19 18:23:14 +00:00
armop.inc	+ SVC instruction	2013-03-24 20:22:06 +00:00
armreg.dat	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
armtab.inc	Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)	2012-10-19 18:23:14 +00:00
cgcpu.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
cpubase.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
cpuelf.pas	+ ELF linker back-ends for ARM and MIPS.	2013-01-13 18:05:19 +00:00
cpuinfo.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
cpunode.pas
cpupara.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
cpupi.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
cputarg.pas	* Sync with trunk r23404.	2013-01-16 13:21:51 +00:00
hlcgcpu.pas
itcpugas.pas	* remove unused units from uses statements	2013-01-03 23:07:09 +00:00
narmadd.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
narmcal.pas	* moved ARM/x86 ifdef'ed code from ncgcal to virtual methods	2013-04-07 13:42:06 +00:00
narmcnv.pas	+ support for LOC_(C)MMREGISTER in hlcg	2013-05-31 12:05:14 +00:00
narmcon.pas	* remove unused units from uses statements	2013-01-03 23:07:09 +00:00
narminl.pas	+ support for LOC_(C)MMREGISTER in hlcg	2013-05-31 12:05:14 +00:00
narmmat.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
narmmem.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
narmset.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00
pp.lpi.template
raarm.pas
raarmgas.pas	Add support in ARM assembler reader for ldr reg, =literal syntax	2013-07-21 16:06:57 +00:00
rarmcon.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmdwa.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmnor.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmnum.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmrni.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmsri.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmsta.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmstd.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rarmsup.inc	+ Cortex-M3 special registers, resolves #23185	2012-10-21 20:06:07 +00:00
rgcpu.pas	+ arm: tsettings.instructionset	2013-08-25 21:56:12 +00:00