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Improve loading of ARM constant values

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*  use split_into_shifter_const to reduce the MOV/ORR combination to a
   single check and allow a broader rang of combinations.
*  Introduce MVN/BIC combination to load values which have more 1 than 0
   bits set (like small negative values)

git-svn-id: trunk@21646 -
This commit is contained in:
masta 2012-06-18 16:59:24 +00:00
parent d987cee96a
commit f11fbe527e
1 changed files with 8 additions and 11 deletions
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19
compiler/arm/cgcpu.pas
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@ -253,6 +253,7 @@ unit cgcpu;
imm_shift : byte;
l : tasmlabel;
hr : treference;
imm1, imm2: DWord;
begin
if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
internalerror(2002090902);
@ -261,20 +262,16 @@ unit cgcpu;
else if is_shifter_const(not(a),imm_shift) then
list.concat(taicpu.op_reg_const(A_MVN,reg,not(a)))
{ loading of constants with mov and orr }
else if (is_shifter_const(a-byte(a),imm_shift)) then
else if (split_into_shifter_const(a,imm1, imm2)) then
begin
list.concat(taicpu.op_reg_const(A_MOV,reg,a-byte(a)));
list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,byte(a)));
list.concat(taicpu.op_reg_const(A_MOV,reg, imm1));
list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg, imm2));
end
else if (is_shifter_const(a-word(a),imm_shift)) and (is_shifter_const(word(a),imm_shift)) then
{ loading of constants with mvn and bic }
else if (split_into_shifter_const(not(a), imm1, imm2)) then
begin
list.concat(taicpu.op_reg_const(A_MOV,reg,a-word(a)));
list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,word(a)));
end
else if (is_shifter_const(a-(dword(a) shl 8) shr 8,imm_shift)) and (is_shifter_const((dword(a) shl 8) shr 8,imm_shift)) then
begin
list.concat(taicpu.op_reg_const(A_MOV,reg,a-(dword(a) shl 8) shr 8));
list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,(dword(a) shl 8) shr 8));
list.concat(taicpu.op_reg_const(A_MVN,reg, imm1));
list.concat(taicpu.op_reg_reg_const(A_BIC,reg,reg, imm2));
end
else
begin