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basemath
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191 Commits

Author SHA1 Message Date
Nikolay Nikolov
2e65a5d458 + introduced cgbase.topcg2str and topcmp2str for converting TOpCg and TOpCmp to strings (useful for debug logging, etc) 2024-04-07 22:10:41 +03:00
Nikolay Nikolov
11712658b0 + implemented WebAssembly code generator support for funcref and externref data 
types, using new register types R_FUNCREFREGISTER and R_EXTERNREFREGISTER
 2023-06-07 05:25:57 +03:00
Jinyang He
12c4290ffe Add loongarch64 architecture support to compiler 2023-02-05 19:18:48 +00:00
Jonas Maebe
e2ade64a1e cgbase: make first parameter of supregset_reset "out" 2022-10-12 22:58:18 +02:00
Nikolay Nikolov
557e823734 + introduced trefaddr.addr_got_tls, to be used for generating WebAssembly threadvar access, when WASM multithreading is turned on 2022-07-14 00:28:03 +03:00
florian
8006900e8e - clean up 
git-svn-id: trunk@49399 -
 2021-05-24 09:26:44 +00:00
florian
e047e7db91 + RiscV: initial support of pic generation 
git-svn-id: trunk@48947 -
 2021-03-13 16:18:00 +00:00
Jonas Maebe
9376f5a43a * AArch64: added SIMD instructions (only plain ARMv8-A for now) 
o added AArch64 regset parsing support in assembler reader, means that "{"
     no longer starts comments there (like in the ARM assembler reader)
   o added AArch64 indexed SIMD register support and removed old cg hacks
     that worked around its absence

git-svn-id: trunk@47116 -
 2020-10-15 20:29:36 +00:00
yury
e6b89c98f5 * Changed tsuperregisterworklist.get() to always return the last item from the list. 
* Reversed sort order of simplifyworklist so nodes with most interferences will get their colors first.
    Since degree of nodes in simplifyworklist before sorting is always
    less than the number of usable registers this should not trigger spilling
    and should lead to a better register allocation in some cases.

  After these changes sysutils.o for i386-win32 is 80 bytes less. :)

git-svn-id: trunk@45857 -
 2020-07-25 18:29:59 +00:00
florian
cb11e2568d + Xtensa: patch by Christo Crause to add optional MAC16 registers, resolves #37130 
git-svn-id: trunk@45679 -
 2020-06-22 19:05:13 +00:00
nickysn
b98cc1ebff + added subregisters for the Z80 flags 
git-svn-id: trunk@45341 -
 2020-05-11 18:03:29 +00:00
Jonas Maebe
3f6ad30b69 * don't convert the fpu parameters size from tcgsize -> int -> float_tcgsize 
if not required, to avoid translating OS_C64 into OS_F64 (fix for x86
    test failures after r45205)

git-svn-id: trunk@45221 -
 2020-05-02 13:17:21 +00:00
nickysn
4e5eb7fa4e + implemented tcgz80.a_loadaddr_ref_reg for symbol references 
git-svn-id: branches/z80@44682 -
 2020-04-11 01:00:46 +00:00
florian
70a836c4a2 * first part of merging parts of Jeppe's intrinsics patch, mainly r31135 
is merged by this commit with a lot of adaptions

git-svn-id: trunk@43949 -
 2020-01-14 21:52:39 +00:00
florian
b7c6e01b03 * cleaning up tcgsize: it makes no sense to declare every combination and type 
the different vector types must be either handled in the high level cg or
    by using the shuffle parameter

git-svn-id: trunk@43860 -
 2020-01-04 21:54:53 +00:00
Jonas Maebe
9bd33f7a45 + support for LLVM metadata constant string parameters 
o they are implemented as a new metadata register class, whereby the
     subregister indicates the metadata type (currently always a string)
     and the superregister is an index in the metadata array (which
     contains the strings). LLVM metadata can only be passed as parameters
     to intrinsics in bitcode, so moves of metadata into other registers
     triggers internal errors and when moving them into parameters, we
     replace the parameter's register with the metadata register (and look
     up the corresponding string when writing out the bitcode)

git-svn-id: trunk@43816 -
 2019-12-30 15:04:57 +00:00
florian
16163b74ec + support for the gnu2 general-dynamic tls model on arm, use it instead of the gnu one as the gnu2 one can be relaxed (access optimizations by the linker) 
+ support pic relocations in the internal assembler writer

git-svn-id: trunk@43128 -
 2019-10-05 20:48:26 +00:00
florian
03dfc615dc + new relocations for arm tls 
git-svn-id: trunk@43123 -
 2019-10-05 20:48:21 +00:00
florian
69786ffe73 somehow committing went wrong, second part of last commit: 
+ AArch64: support for vX.8b/vX.16b register names
+ support for more than 256 registers in the register dat files
- removed totherregisterset
+ AArch64: use vmov to load immediates if possible
+ AArch64: use eor to clear mm registers

git-svn-id: trunk@42917 -
 2019-09-03 21:07:33 +00:00
Jonas Maebe
b1a41aa5b8 * fixed NR_INVALID declaration 
git-svn-id: trunk@42274 -
 2019-06-23 14:12:28 +00:00
florian
597a23d278 + tls support for x86_64-linux (not yet enabled by default) 
git-svn-id: trunk@41081 -
 2019-01-27 09:37:25 +00:00
florian
063415fa72 + i386-linux support for tls-based threadvars 
git-svn-id: trunk@40272 -
 2018-11-07 22:03:02 +00:00
florian
9f16c34329 + initial work for tls-based threadvar support on arm-linux 
git-svn-id: trunk@40267 -
 2018-11-07 22:02:58 +00:00
Jeppe Johansen
ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 
git-svn-id: branches/laksen/riscv_new@39474 -
 2018-07-20 08:21:15 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton 
+ tests

git-svn-id: trunk@38206 -
 2018-02-11 17:50:37 +00:00
florian
5e969d90cb + SPARC64 cpugas unit 
+ support for %gdop_hix22/%gdop_lox22

git-svn-id: trunk@36475 -
 2017-06-10 11:24:55 +00:00
florian
1f4432af6b * sparc64 compiler can be build, not working yet 
git-svn-id: trunk@36399 -
 2017-06-02 20:13:30 +00:00
nickysn
c8487c4150 + added individual bits of the x86 flags register as subregisters 
git-svn-id: trunk@35955 -
 2017-04-26 13:52:52 +00:00
svenbarth
c8202061dc * get rid of addr_load_indirect again by having tcgx86 provide an internal implementation of both make_simple_ref() and a_load_ref_reg() so that make_direct_ref() can call the latter (and the latter the former) without fear of inifinite recursive calls due to the symbol; a_load_ref_reg() is additionally declared as "final" as a_load_ref_reg_internal() needs to be overloaded instead (which is the case for tcg8086) 
git-svn-id: trunk@34579 -
 2016-09-30 14:01:02 +00:00
Jonas Maebe
27bb656cec * replaced "in_make_direct_ref" field with a trefaddr flag 
git-svn-id: trunk@34548 -
 2016-09-20 21:43:52 +00:00
nickysn
0fdc62e0f7 + initialize DS with the current unit's data segment in the function entry code 
generated in the huge memory model

git-svn-id: trunk@31500 -
 2015-09-03 21:44:16 +00:00
florian
4d01271944 * due to avr's harvard architecture, loads of code labels need to use the gs(...) macro 
git-svn-id: trunk@30559 -
 2015-04-12 20:29:13 +00:00
Jonas Maebe
67b8aceaee * synchronized with privatetrunk till r30095 
git-svn-id: branches/hlcgllvm@30101 -
 2015-03-05 20:32:15 +00:00
Jonas Maebe
7fc9d775df + support for @page and @pageoffs addressing on AArch64: these are PIC 
references that directly take the address of a symbol, rather than
    of its GOT entry
   o use these addressing modes to access local symbols

git-svn-id: trunk@29932 -
 2015-02-23 22:53:43 +00:00
Jonas Maebe
123503a4f7 + GOT-related (Darwin) address modes 
git-svn-id: trunk@29847 -
 2015-02-23 22:49:10 +00:00
Jonas Maebe
67c9d60b72 * factored out the check regarding whether the index of a vecn needs to be 
loaded into a register because of its size
   o by default, also allow if the size is the same as OS_ADDR but with a
     different sign

git-svn-id: trunk@29827 -
 2015-02-23 22:48:08 +00:00
Jonas Maebe
bacd303208 * synchronized with trunk up to r27758 
git-svn-id: branches/hlcgllvm@27779 -
 2014-05-12 16:12:34 +00:00
nickysn
ec6dfb5853 + added tcgsize2str function 
git-svn-id: trunk@27453 -
 2014-04-03 16:50:50 +00:00
sergei
9c54cdc85d * x86: Cleaned out addr_far,addr_far_ref used to encode far calls/jumps. NASM (and FPC x86 assembler based on it) already have opsize=S_FAR for this purpose. 
git-svn-id: trunk@27037 -
 2014-03-08 22:54:43 +00:00
Jonas Maebe
1df3039424 + LLVM temp allocator based on new R_TEMPREGISTER register class. For every 
temp we allocate, we set the base register to a newly allocated
    R_TEMPREGISTER. This allows for uniquely identifying a temp even if its
    offset is modified.

git-svn-id: branches/hlcgllvm@26033 -
 2013-11-11 11:14:59 +00:00
florian
4148637c8c * fold mov/lea/mov as well if possible 
git-svn-id: trunk@25905 -
 2013-11-01 19:01:29 +00:00
Jonas Maebe
2ba22f666e + support for R_SUBMMX and R_SUBMMY in generic_regname() 
git-svn-id: trunk@25225 -
 2013-08-07 12:41:47 +00:00
nickysn
9dbbffba61 + added trefaddr.addr_seg for referencing the segment of a symbol 
git-svn-id: trunk@24859 -
 2013-06-10 01:16:37 +00:00
nickysn
604b7c9deb + added cg.a_call_ref_near and a_call_ref_far 
git-svn-id: trunk@24853 -
 2013-06-09 20:22:47 +00:00
nickysn
2279e51a95 + added trefaddr.addr_far for emitting far calls 
git-svn-id: trunk@24826 -
 2013-06-09 10:24:06 +00:00
nickysn
c2e3fb5918 + emit proper interrupt procedure entry/exit code on i8086 
git-svn-id: trunk@24728 -
 2013-06-01 15:50:11 +00:00
nickysn
8d6017348a * fixed the defines of OS_PAIR and OS_SPAIR for cpus with 16-bit or 8-bit ALU 
git-svn-id: branches/i8086@23797 -
 2013-03-12 01:00:40 +00:00
sergei
a519741d89 - Revert {$J-} accidentally committed in r23555. 
git-svn-id: trunk@23556 -
 2013-02-01 16:49:46 +00:00
sergei
503b132096 * cgbase.pas: added more MIPS-specific address types, needed to support large GOT model. 
* cpugas.pas: GetReferenceString: rewritten, it is easier than trying to fix it. Fixes incorrect writing of non-PIC references containing base, symbol and offset together, and some forms of PIC references. Also supports newly introduced address types.

git-svn-id: trunk@23555 -
 2013-02-01 16:46:22 +00:00
pierre
493c77bca0 + Add addr_pic_call16 relocation type for mips 
git-svn-id: trunk@23547 -
 2013-01-31 13:08:49 +00:00