florian
c7290bfb78
* enclose {$define DEBUG_AOPTCPU} in {$ifdef EXTDEBUG}
2025-03-10 22:50:49 +01:00
florian
46dcffed42
* MIPS64: make use of DMTC1 instruction
2024-10-18 21:53:26 +02:00
Pierre Muller
e8c6274915
Add -msoft-float or -mhard-float option to GNU assembler calls
2024-10-01 22:27:32 +01:00
Nikolay Nikolov
b077d17cdd
* MIPS: don't generate FPU code for int to real conversion when FPU emulation is enabled
2024-09-29 20:56:43 +03:00
Nikolay Nikolov
bf7bf44727
* MIPS: don't generate FPU code for abs(real), sqr(real) and sqrt(real) in case
...
FPU emulation is enabled
2024-09-29 20:48:38 +03:00
Nikolay Nikolov
7b02331168
+ added fpu_libgcc to MIPS
2024-09-29 20:24:31 +03:00
Nikolay Nikolov
180c23b395
* MIPS code gen: don't use FPU registers for function parameters in case SoftFPU
...
is enabled
2024-09-29 20:14:55 +03:00
Nikolay Nikolov
00d86d24be
* MIPS code generator: don't put floating point results in FPU registers for
...
function results, if the SoftFPU is enabled
2024-09-29 20:11:47 +03:00
Kirill Kranz
be9bfbecc5
typo fixed
2024-09-29 16:59:02 +03:00
Kirill Kranz
8e6a8a36cd
case statiment insteed of ifs
2024-09-29 16:58:12 +03:00
Kirill Kranz
d1438e0d39
check if next instruction exists
2024-09-29 16:58:12 +03:00
Kirill Kranz
e9d8bcf484
hlcgcpu.pas: uses unit systems + t_ps1.pas: correct Message3
2024-09-29 16:58:12 +03:00
Kirill Kranz
530a962dfc
thx god You seen it! (reverse)
2024-09-29 16:58:12 +03:00
Kirill Kranz
14ad18a82b
leave PIC code unchanged
2024-09-29 16:58:12 +03:00
Kirill Kranz
b47687852e
if taicpu(p).opcode in [....] beautiy fix
2024-09-29 16:58:12 +03:00
Kirill Kranz
034c361804
resolveReadAfterWrite moved to aasmcpu.pas
2024-09-29 16:58:12 +03:00
Kirill Kranz
17c0765655
Indentation
2024-09-29 16:58:12 +03:00
Kirill Kranz
2f5cbbacb7
DynArrays works
...
because of InitHeap3, malloc3 and free3 functions from the psy-q-sdk
2024-09-29 16:58:12 +03:00
Kirill Kranz
ec2f18f8be
compiles cube.pas example
2024-09-29 16:56:18 +03:00
Kirill Kranz
52651a7ede
First compiler Build
2024-09-29 16:56:18 +03:00
Sven/Sarah Barth
f584c559fd
* fold the MIPS tabitype into tabi as the former wasn't really used or hooked up anyway; this way the ABI can be set using -Ca<abi>
2024-06-04 23:45:46 +02:00
florian
f49da05633
* unified g_concatcopy_move
2024-05-15 22:52:24 +02:00
Pierre Muller
dc04a8a677
Fix storing of unaligned 64-bit to memory
2023-04-21 10:32:13 +01:00
Pierre Muller
d18ff64ed7
Fix a_load64_reg_ref and a_load64_ref_reg mips methods
2022-11-07 22:24:34 +00:00
Pierre Muller
c96bb0f416
Handle unaligned references in 64-bit a_load_ref_reg and a_load_reg_ref methods
2022-11-06 22:14:38 +00:00
Pierre Muller
b8920670f4
Change is_macro to return true for A_JAL if in pic mode
2022-09-20 22:33:14 +01:00
florian
85c7368759
* handle also simulated flags in tmipselnotnode.second_boolean, resolves #39877
2022-08-24 21:16:23 +02:00
florian
9c72ab651d
* use g_concatcopy_unaligned on MIPS if needed
2022-08-06 15:04:35 +02:00
florian
d153c75e84
* small MIPS64 fix
2022-06-13 23:07:43 +02:00
florian
9201047f31
* a few more MISP64 fixes
2022-06-11 23:09:15 +02:00
florian
4149562787
* more MIPS64 fixes
2022-06-10 23:20:38 +02:00
florian
8bd1f19639
* few MIPS64 fixes
2022-06-09 22:55:24 +02:00
florian
27fb9086aa
* cleanup: cs_opt_loopunroll is a generic optimization for a long time already
2022-03-08 23:03:18 +01:00
Pierre Muller
b048ae37b2
Fix loading of 64-bit constant into register for 64-bit mips CPU
2022-02-15 19:51:26 +00:00
florian
ba51494bd7
* more MIPS64 fixes
2022-02-09 22:59:46 +01:00
florian
bbece3e668
* MIPS64 can
...
* MIPS64 does not need separate 64 bit code path for ordinals
2022-02-08 23:08:32 +01:00
Florian Klämpfl
9348f58e70
* cosmetics
2022-02-06 20:13:51 +01:00
Pierre Muller
a9c67f22fd
Add use of SD instruction in tcgmips.a_load_reg_ref method
2022-02-04 22:54:58 +00:00
Pierre Muller
c2ffd51c63
Fix compilation from 32-bit CPU by avoiding use of aint variable in for loop
2022-02-04 18:32:49 +00:00
florian
b2e553d3c4
* mips64el compiler can be compiled
2022-02-03 23:15:34 +01:00
florian
03f4685455
+ sanity checks in mips and sparc register allocator
2021-12-17 21:25:17 +01:00
florian
6404478ea4
* cleanup of VER3_0 defines
2021-11-17 22:19:57 +01:00
florian
ff3acfb8cd
* cleanup of 2.7.0 defines
2021-10-31 13:20:28 +01:00
pierre
75a9c5b500
Also avoid invalid typecast for RegLoadedWithNewValue method for mips, sparcgen and xtensa
...
git-svn-id: trunk@49186 -
2021-04-12 08:57:23 +00:00
pierre
01a351f804
Fix for bug report 38549 about wrong code generation
...
for mips/mipsel and riscv32/riscv64 CPUs for
set operators '<=' and '>='.
New tests for this bug report.
tw38549.pp, main source, also included
by tw38549a.pp, tw38549b.pp, tw38459c.pp and tw38459d.pp
with explicit {$packset X}, with X=1,2,4, or 8 added.
git-svn-id: trunk@48874 -
2021-03-03 22:15:20 +00:00
florian
637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
...
git-svn-id: trunk@47103 -
2020-10-13 19:59:01 +00:00
florian
28f25b2df0
* reworked usage of tcgnotnode.handle_locjump
...
git-svn-id: trunk@46275 -
2020-08-05 21:15:32 +00:00
yury
cc936710a0
* mips: Added support for unaligned load/store. It greatly improves performance and prevents bus errors on systems which do not emulate unaligned memory access.
...
git-svn-id: trunk@45871 -
2020-07-28 20:08:41 +00:00
yury
6478a727d7
* Fixed the peephole optimization of conditional movs for mips.
...
git-svn-id: trunk@45826 -
2020-07-22 11:40:21 +00:00
pierre
0c6998bb11
Try to fix mipsel-android by making sure P does not point to a freed instruction
...
git-svn-id: trunk@45812 -
2020-07-19 21:21:18 +00:00
