Commit Graph

49 Commits

Author SHA1 Message Date
florian
4eb8f8e565 * patch by Marģers
- Rename 3DNow instruction (fixed long lasting typo in mnemonic). PMULHRWA  --> PMULHRW
    - Add vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq, vpclmulhqhqdq.
    - Fix "typo" for SHA1MSG2
2024-05-30 21:49:30 +02:00
florian
6c7e6191f6 + support of SHA extension in the internal assembler 2021-10-09 15:44:46 +02:00
florian
fc960879de -- Zusammenführen von r47033 bis r47401 in ».«:
C    compiler/i386/i386nop.inc
U    compiler/i386/i386tab.inc
U    compiler/i386/i386atts.inc
U    compiler/i386/i386att.inc
C    compiler/i8086/i8086nop.inc
U    compiler/i8086/i8086tab.inc
U    compiler/i8086/i8086atts.inc
U    compiler/i8086/i8086att.inc
U    compiler/x86/x86ins.dat
C    compiler/x86/rax86.pas
U    compiler/x86/aasmcpu.pas
U    compiler/x86/cpubase.pas
U    compiler/x86/agx86att.pas
U    compiler/x86/itcpugas.pas
U    compiler/x86/rax86att.pas
C    compiler/x86_64/x8664nop.inc
U    compiler/x86_64/x8664tab.inc
U    compiler/x86_64/x8664ats.inc
U    compiler/x86_64/x8664att.inc
U    compiler/utils/mkx86ins.pp
U    tests/utils/avx/asmtestgenerator.pas
U    tests/utils/avx/avxopcodes.pas
-- Aufzeichnung der Informationen für Zusammenführung von r47033 bis r47401 in ».«:
 U   .
Konfliktübersicht:
  Textkonflikte: 4
Konfliktübersicht:
  Textkonflikte: 4

git-svn-id: trunk@47402 -
2020-11-12 20:31:29 +00:00
tg74
c65b042856 bugfix opcodes cvt.., vcvt.. memory operands and typesize
git-svn-id: branches/tg74/avx512-0037785@47113 -
2020-10-15 08:22:29 +00:00
florian
963fe73d19 + support all XSAVE instructions, resolves #37864
git-svn-id: trunk@47042 -
2020-10-03 14:51:31 +00:00
tg74
1454e8b29d new avx512-opcodes VBMI2,VNNI,BITALG ...
git-svn-id: branches/tg74/avx512merge@43406 -
2019-11-06 19:51:01 +00:00
florian
746bfced25 Synchronized with trunk, part 1 (only make cycle tested, make all is broken, avx-512 support not yet tested
git-svn-id: branches/tg74/avx512@42642 -
2019-08-10 13:53:20 +00:00
florian
4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799
+ avxopcodes tests also movbe and pclmulqdq

git-svn-id: trunk@40951 -
2019-01-20 18:50:12 +00:00
florian
8943c0584e + patch by J. Gareth Moreton to support BMI2 instructions
+ extended avx test generator with the newly added BMI2 instructions

git-svn-id: trunk@39875 -
2018-10-07 10:10:19 +00:00
tg74
dd967ecfee remove any gather/scatter opcodes for nights mill
git-svn-id: branches/tg74/avx512@39742 -
2018-09-12 09:59:04 +00:00
tg74
c611e4814a new avx512 opcodes
git-svn-id: branches/tg74/avx512@39720 -
2018-09-10 06:19:45 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes
git-svn-id: branches/tg74/avx512@39705 -
2018-09-03 05:40:44 +00:00
tg74
914e31dbd1 new AVX512 instructions vextracti..,vextractf..
git-svn-id: branches/tg74/avx512@39674 -
2018-08-27 06:06:27 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512
git-svn-id: branches/tg74/avx512@39636 -
2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register
git-svn-id: branches/tg74/avx512@39457 -
2018-07-16 17:06:57 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd.
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
2018-03-03 23:32:54 +00:00
marco
f21a141144 * mantis #32001, add 32 vcmpps variants.
git-svn-id: trunk@38403 -
2018-03-03 23:10:03 +00:00
nickysn
ae92973196 + added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and
retfq x86 instructions. These are variants of the ret instruction with the
  return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
  a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
  32-bit offset, followed by a 16-bit segment), etc.

git-svn-id: trunk@37571 -
2017-11-10 16:53:29 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
2017-10-12 00:07:02 +00:00
florian
48fbd569fd * support for the CDQE instruction, by Emelyanov Roman, resolves #30978
git-svn-id: trunk@34982 -
2016-11-27 12:42:22 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
git-svn-id: trunk@34917 -
2016-11-18 20:19:39 +00:00
florian
406e3c4ac1 + support xgetbv instruction, resolves issue #29958
git-svn-id: trunk@33418 -
2016-04-03 20:53:10 +00:00
florian
8d5cc3dfa4 * (extended and modified) patch by Emelyanov Roman to add suport of RDRAND, RDSEED and TSX instructions set, resolves issue #29893.
In comparison with the original patch, support for a i386 has been added as well as a test program. 
  Further, a small issue with xbegin has been fixed

git-svn-id: trunk@33375 -
2016-03-28 19:08:13 +00:00
florian
a3964d9ee0 + support for RDTSCP, resolves issue #28916
git-svn-id: trunk@32652 -
2015-12-13 13:28:51 +00:00
florian
d6e4af8279 + applied remaining patches of Torsten Grundke: adds gather instructions of avx2
git-svn-id: trunk@29745 -
2015-02-17 21:43:46 +00:00
sergei
dc628b8969 * x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
git-svn-id: trunk@27934 -
2014-06-11 22:31:40 +00:00
florian
842e027a9f + prove of concept how FMA4 could be supported in inline assembler
git-svn-id: trunk@27214 -
2014-03-20 21:25:38 +00:00
florian
a79be2b05c + support for FMA instructions in inline assembler
+ extended avx test code with FMA

git-svn-id: trunk@27209 -
2014-03-20 20:06:56 +00:00
florian
aa107b914c * merged avx2 branch, developed by Torsten Grundke
git-svn-id: trunk@27200 -
2014-03-20 12:03:52 +00:00
florian
7028210817 + tzcnt assembler instruction
git-svn-id: trunk@26506 -
2014-01-18 12:11:50 +00:00
nickysn
f6e846c574 + added the NEC V20/V30 instructions
git-svn-id: trunk@25750 -
2013-10-11 21:27:56 +00:00
florian
9b6094a58c + added a few BMI instructions to see if they can be encoded
git-svn-id: trunk@24907 -
2013-06-16 09:35:21 +00:00
florian
283ff05127 * merged avx support in inline assembler developed by Torsten Grundke
git-svn-id: trunk@22568 -
2012-10-06 19:47:18 +00:00
florian
c011949765 + iretq for x86_64
git-svn-id: trunk@18273 -
2011-08-19 12:56:26 +00:00
sergei
0231863fce + Added missing PMULLD instruction, part of Mantis #19910
git-svn-id: trunk@18106 -
2011-08-06 06:59:33 +00:00
sergei
3b979fef6d * Re-commit r17437 after more testing and fixing aasmcpu.pp in r17449.
git-svn-id: trunk@17452 -
2011-05-14 11:04:52 +00:00
sergei
b257231203 * Revert r17437, it breaks builds with -O2 and builds on i386 (although -O- on x86_64 is ok).
git-svn-id: trunk@17439 -
2011-05-12 23:53:18 +00:00
sergei
1d81a1244b A big update of x86 instruction table, part 1 (mostly SIMD instructions):
* Using ot_mmxrm and ot_xmmrm operand types to match arguments, reduces number of required entries by half.
* Replaced all literal $66, $F2 and $F3 prefixes with control codes (\361, \334 and \333, respectively).
* Prefix control codes imply writing REX, so code \323 after them is no longer necessary, removed.
* Fixed technology flags (SSSE3, SSE4.1, SSE4.2)
- Removed codes \300 and \301 (intended to generate address size prefix). FPC does not support this feature (the prefix itself is generated, but process_ea rejects operands needing non-default address size). Probably we don't even need to support it. But if we do, a much simpler solution is check all operands, like today's NASM does.
* Fixed/added some instructions along the way, namely CRC32, UNPCKHPD, CMPNEQSD.

git-svn-id: trunk@17437 -
2011-05-12 19:49:19 +00:00
sergei
6739cec2b9 * Flagged with NOX86_64 instructions/encodings that are invalid in 64-bit mode.
* AESKEYGENASSIST is not ATT-specific name, it is used by Intel-style assemblers as well. Also updated tests/test/taes1.pp to reflect the change.
+ Added SCASQ, resolves #16730 (other opcodes mentioned in that report were added/fixed earlier)

git-svn-id: trunk@17431 -
2011-05-11 15:50:59 +00:00
pierre
af32b57170 * increase op2strtable size to string[15] and rectify askeygen to askeygenassist for ATT
git-svn-id: trunk@17358 -
2011-04-21 13:38:20 +00:00
florian
9279c6955e * support for SSSE3, SSE4,1, SSE4.2, AES instructions set by Emelyanov Roman, resolves #18527
+ test for aes support

git-svn-id: trunk@17256 -
2011-04-05 20:22:57 +00:00
Jonas Maebe
9273856e84 * disallow pusha*/popa* for x86_64 (mantis #14862)
* disallow pushfd/popfd for x86_64 (mantis #14862)
  * fixed assembling popfq with the internal assembler (it needs a rex.w
    prefisx, while pushfq doesn't)
  * changed the default opcode size of pushf/popf/pusha/popa in
    {$asmmode intel} from "native size" to 16 bit (compatible with Intel
    manuals and Kylix; in AT&T mode, the default size for those operations
    remains the native one)
  * changed pushf/popf in rtl/i386/* into pushfd/popfd because of the
    previous change

git-svn-id: trunk@15546 -
2010-07-10 16:22:46 +00:00
florian
0e96eda236 + some sse4 instructions supported, resolves #9046
git-svn-id: trunk@7613 -
2007-06-09 19:45:06 +00:00
florian
a19ed91cc3 * fix for jcxz, jecxz and jrcxz on 64 bit platforms
git-svn-id: trunk@6400 -
2007-02-10 21:05:27 +00:00
florian
2da51bce72 + cmpxchg16b
git-svn-id: trunk@6095 -
2007-01-21 11:04:19 +00:00
florian
5ece7cbc2f * first part of x86-64 assembler
git-svn-id: trunk@2824 -
2006-03-09 22:05:16 +00:00
florian
588e2c38bf * dwarf branch merged 2004-06-16 20:07:06 +00:00
peter
e6929a1a32 * more x86_64 parameter fixes
* tparalocation.lochigh is now used to indicate if registerhigh
    is used and what the type is
2004-02-09 22:14:17 +00:00
florian
412072f71d * renamed instruction tables 2004-01-15 13:57:58 +00:00