produce the consistent order of elements.
This fixes occasional differences in the register allocation caused by
the address space randomization. When ASLR is in effect, the previous
approach to sort elements by their memory addresses can't guarantee the
consistent elements order for each compilation of the same source code.
in registers.
* Removed superfluous condition in trgobj.enable_moves().
* Fixed flags checking in trgobj.adjacent_ok().
* Added assembler comments about coalescing when DEBUG_SPILLCOALESCE is defined.
- no spill temp is allocated;
- no load of a stack parameter to a spill temp;
- if a stack parameter is used only once do not preload it to a register. The parameter can be accessed directly in the stack if the target CPU supports this.
git-svn-id: trunk@46776 -
- Do not use count_uses, since weight already represents a usage count of a register.
- Do not count spills of registers with weight less than 100.
git-svn-id: trunk@46775 -
It is pointless to keep them for further processing. Also it may
cause endless spilling.
This can happen when compiling for very constrained CPUs such as
i8086 where indexed memory access instructions allow only
few registers as arguments and additionally the calling convention
provides no general purpose volatile registers.
git-svn-id: trunk@46199 -
* Do not coalesce registers 'u' and 'v' if 'u' is the last usable real register available for imaginary register 'n' which also interferences with 'v'.
This prevents endless spilling in some cases for constrained CPUs such as AVR. Resolves issue #37421.
Also this reduces the number of spilled registers in some cases and even eliminates spilling completely for some simple routines for i386 and AVR.
* Added a debug output of the number of spilled registers for each routine. This allows to easily compare results after changes in spilling algorithms.
git-svn-id: trunk@45987 -
* Reversed sort order of simplifyworklist so nodes with most interferences will get their colors first.
Since degree of nodes in simplifyworklist before sorting is always
less than the number of usable registers this should not trigger spilling
and should lead to a better register allocation in some cases.
After these changes sysutils.o for i386-win32 is 80 bytes less. :)
git-svn-id: trunk@45857 -
This fixes the register allocation for i8086 when handling registers for very constrained instructions such as "mov ireg1,[ireg2+ireg3]".
Here ireg2 can be only BX or BP. So in most cases only BX is available. When ireg2 is spilled, its value must be loaded to BX only.
Coloring of the ireg which holds the spilled value must be as early as possible to be able to assign BX to this ireg.
This fix should also help register allocation for other constrained/old CPUs.
git-svn-id: trunk@45843 -
