default segment base for the ref, in case there's no segment override
* in the internal assembler, use get_default_segment_of_ref to strip redundant
prefixes, instead of always assuming all refs are DS-based
git-svn-id: trunk@37486 -
* when generating x86 code for parameterized string instructions with the
internal object writer, don't rely on the destination operand being [(r/e)di]
when determining the segment prefix, because when using intel syntax, source
and destination can be anything (only the operand size, the address size and
the source segment is taken into account)
git-svn-id: trunk@37452 -
is_x86_parameterless_string_instruction_op and
is_x86_parameterized_string_instruction_op by removing 'instruction' from
their names
git-svn-id: trunk@37451 -
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
with the 186+ 'ins' instruction.
git-svn-id: trunk@37446 -
* changed most of the variables in the assembler readers used to store constants from aint to tcgint
as aint has only the size of the accumular while some CPUs (AVR) allow larger constants in instructions
+ allow access to absolute symbols with address type in inline assembler
* allow absolute addresses in avr inline assembler
+ tests
git-svn-id: trunk@37411 -
o separate information for reading and writing, because e.g. in a
try-block, only the writes to local variables and parameters are
volatile (they have to be committed immediately in case the next
instruction causes an exception)
o for now, only references to absolute memory addresses are marked
as volatile
o the volatily information is (should be) properly maintained throughout
all code generators for all archictures with this patch
o no optimizers or other compiler infrastructure uses the volatility
information yet
o this functionality is not (yet) exposed at the language level, it
is only for internal code generator use right now
git-svn-id: trunk@34996 -
pint type, which is now deprecated (as it does not always represent the
correct pointer type in all i8086 memory models); replacements methods, which
should be used instead are .create_sizeint, .create_int_dataptr or
.create_int_codeptr (or their _unaligned counterparts)
git-svn-id: trunk@34838 -
create constants, corresponding to the SizeInt type for the current target and
are intended to eventually replace .Create_pint, since the pint type is now
deprecated (because it does not correspond to the size of a pointer in certain
i8086 memory models).
git-svn-id: trunk@34620 -
tasmdata.DefineAsmSymbol() and all routines that call it
o will be used to automatically generate AB_INDIRECT sybols when
necessary
git-svn-id: trunk@34164 -
compiler's internal assembly representation. It is not yet generated by the
compiler and is only implemented properly in the NASM writer (but will
eventually be implemented in the other assembler writers as well, including
the internal assembler). In the future, it is intended to allow:
1) catching instructions, generated by the compiler and not supported by the
target CPU, due to a bug in the code generator
2) allowing a different instruction set to be used in inline asm blocks (I'm
planning a new directive for that - {$asmcpu XXX}), because the code
generator will be able to switch target CPU in the middle of the asm output
stream
git-svn-id: trunk@33121 -
* generate code to load the TOC register if it's required, and
emit the the ".localentry" directive to indicate to the linker
where the actual function body starts
* support the ".localentry" directive in the ppc64 assembler reader
o disable the fpc_qword_to_double() assembler implementation for
ELFv2, because we can't manually insert the .localentry directive
before the stack allocation code
* perform indirect calls on ppc64 via R12 in ncgcal, as R12 needs to
contain the function address on entry on ppc64/ELFv2 (and it's
a volatile register, so there's no problem with always using
it)
git-svn-id: trunk@30198 -
backend (required for inserting bitcasts/ptrtoint/... operations inside
typed constant declarations)
o taillvm constructors for creating bitcast-style and getlementptr
operations that accept a tai as their source/base operand
git-svn-id: branches/hlcgllvm@28112 -
to free up space for more ait_* types in taitype (can't have
more than 32 because they have to fit in a small set)
o factored out writing of floating point numbers as an array of
byte in the external assemblers
git-svn-id: branches/hlcgllvm@28105 -
o make use of the fact that callparanodes always first load everything
in temporary parameters (allocated via paramanager.createtempparaloc)
-> we pass those temporary paralocs to the llvm call nodes and ignore
the "real" locations with physical registers
o all function results are forced to memory before handing them back
to the generic code generator to avoid having to deal with special
result locations and llvm<->pascal type differences (llvm removes
the extra temp stores/loads while optimising)
o ideally, the llvm code generator should share the common code with
the generic code generator for a_load_ref_cgpara() at some point in
the future
git-svn-id: branches/hlcgllvm@27013 -
generate declarations when external symbols are referred in a taillvm
instruction
* added "declared" field to tasmsymbol for llvm to make avoid declaring a
symbol multiple times (harmless, but unnecessary)
* all kinds of declarations/definitions are now handled using the new
taillvmdecl, the old separate types have been removed
git-svn-id: branches/hlcgllvm@27010 -
* Change MIPS jump tables in PIC mode to use gp-relative constants, making them ABI-compliant and not requiring dynamic relocations.
git-svn-id: trunk@26886 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
(avoids imaginary register number in "# Var I in register .." assembler comments.
* dbgdwarf.pas : Support register variables as register pairs.
Does not yet handle case of changing registers.
* symsym.pas : add currentregloc field to tabstractnormalvarsym class,
to be able to track changing registers used for a given variable.
* aasmtai.pas : Update currentregloc field of tai_varloc.create sym parameter.
* ncgutil.pas : Only generate a tai_varloc if the new registers are different for the variable.
git-svn-id: trunk@22508 -
and add usermode parsing of LDM/STM ops
This patch basically extends the ARM assembly reader a bit to properly parse CPSR and
SPSR flags for the MSR opcode, and allows the reader to understand
the ^ modifer for register lists for STMxx and LDMxx.
Previously the following combinations weren't possible in straight assembler:
MRS R0, CPSR
MRS R0, SPSR
MSR CPSR_CX, R0
LDMIA SP, {R0-R15}^
etc..
git-svn-id: trunk@22502 -
