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30 Commits

Author SHA1 Message Date
florian
38706a1713 * fix declocked(longint) for aarch64 without LSE, resolves #39569 2022-02-11 23:11:06 +01:00
florian
b0459a19f4 + initial files for intrinsics support on AArch64 2021-11-21 21:11:23 +01:00
florian
4de8ca8393 * fpcr and fpsr are 64 bit on aarch64 
git-svn-id: trunk@49346 -
 2021-05-08 20:10:14 +00:00
Jonas Maebe
3c205f895c * LLVM does not have an intrinsic for int/frac, so don't replace frac with 
a call to runerror(207) there

git-svn-id: trunk@49337 -
 2021-05-04 19:56:22 +00:00
florian
822b460096 * fix bootstrapping on aarch64-linux with 3.2.x 
git-svn-id: trunk@49264 -
 2021-04-25 19:24:18 +00:00
florian
5557dbedf2 + Aarch64: directly inline code for frac(...) 
git-svn-id: trunk@49261 -
 2021-04-25 09:26:47 +00:00
florian
cd3570caf1 + Aarch64: use frintz for int(...) instead of creating a helper call 
git-svn-id: trunk@49260 -
 2021-04-25 08:53:12 +00:00
florian
047d13e7e1 * fpsr and fpcr are 64 bit on aarch64 
git-svn-id: trunk@49257 -
 2021-04-24 14:06:36 +00:00
florian
d53b17cadc + Aarch64: completed LSE support for all interlocked operations 
git-svn-id: trunk@49212 -
 2021-04-16 19:33:31 +00:00
florian
e6f01065ec + Aarch64: use LSE if available for atomic intrinsics 
git-svn-id: trunk@49113 -
 2021-04-03 11:59:36 +00:00
pierre
3362abb30c * Set softfloat_rounding_mode indise SetRoundMode function for all CPUs. 
* SetRoundMode returns previous rounding mode value for all CPUs.

git-svn-id: trunk@48018 -
 2021-01-03 21:44:18 +00:00
svenbarth
5a68b2218a * for Aarch64 inline assembly comments need to start with // 
git-svn-id: trunk@47123 -
 2020-10-18 08:52:41 +00:00
Jonas Maebe
9376f5a43a * AArch64: added SIMD instructions (only plain ARMv8-A for now) 
o added AArch64 regset parsing support in assembler reader, means that "{"
     no longer starts comments there (like in the ARM assembler reader)
   o added AArch64 indexed SIMD register support and removed old cg hacks
     that worked around its absence

git-svn-id: trunk@47116 -
 2020-10-15 20:29:36 +00:00
florian
9a573173dd * Aarch64: fix Math.SetExceptionMask for implementations throwing hardware 
exceptions

git-svn-id: trunk@46880 -
 2020-09-16 20:08:11 +00:00
Jonas Maebe
d9f4c85d2e * llvm sometimes uses the AArch64 framepointer register as a regvar in the 
main routine (because it can never return) -> attempt to guard against
    invalid accesses in get_caller_addr

git-svn-id: trunk@44066 -
 2020-01-29 22:21:21 +00:00
florian
688c7d439f o AArch64: 
* properly initialize FPU
    * FMOV cannot throw an FPU exception

git-svn-id: trunk@43167 -
 2019-10-11 21:55:48 +00:00
florian
078595be4c + support for software floating point exception handling on AArch64 (-CE) 
git-svn-id: trunk@42891 -
 2019-09-01 17:26:11 +00:00
florian
ff86c80176 * cpu specific header file for the system unit: cpuh.inc, moved several declarations into it 
git-svn-id: trunk@37542 -
 2017-11-01 16:33:30 +00:00
Jonas Maebe
2cacb588aa * replaced AArch64 setjmp/longjmp code initially taken from NetBSD with 
straightforward own implementation

git-svn-id: trunk@30006 -
 2015-02-25 19:34:42 +00:00
Jonas Maebe
1edd3ac511 * support for the "RaisePending" parameter of RaiseExceptions on AArch64 
git-svn-id: trunk@29951 -
 2015-02-23 22:55:02 +00:00
Jonas Maebe
41fba0c4f7 * switched to using the stack pointer as base register for the temp allocator 
instead of the frame pointer register:
      1) we exactly know the offsets of the temps from the stack pointer
         after pass 1 (based on the require parameter stack size for called
         routines), while we don't know it for the frame pointer (it depends
         on the number of saved registers)
      2) temp offsets from the stack pointer are positive while those from
         the frame pointer are negative, and we can directly encode much
         bigger positive offsets in the instructions
   o move the stack pointer register to a virtual register in
     loadparentfpn, because many instructions cannot directly operate
     on/with the stack pointer
   o add the necessary register interference edges for the stack pointer
     register

git-svn-id: trunk@29938 -
 2015-02-23 22:54:03 +00:00
Jonas Maebe
65141ab135 + aarch64 makefile.cpu 
git-svn-id: trunk@29887 -
 2015-02-23 22:51:12 +00:00
Jonas Maebe
e32965879d * dummy strings.inc for aarch64 
git-svn-id: trunk@29886 -
 2015-02-23 22:51:09 +00:00
Jonas Maebe
dad442c7e3 + aarch64 fpu init, atomic routines and memory barriers 
git-svn-id: trunk@29885 -
 2015-02-23 22:51:06 +00:00
Jonas Maebe
6813831e03 + AArch64 setjump code based on NetBSD version 
git-svn-id: trunk@29884 -
 2015-02-23 22:51:03 +00:00
Jonas Maebe
6b371315f3 + dummy AArch64 stringss.inc file 
git-svn-id: trunk@29883 -
 2015-02-23 22:51:00 +00:00
Jonas Maebe
e82201d6ac + dummy set.inc for AArch64 
git-svn-id: trunk@29882 -
 2015-02-23 22:50:57 +00:00
Jonas Maebe
4c7f75c93b + round/trunc/int for AArch64 
git-svn-id: trunk@29881 -
 2015-02-23 22:50:54 +00:00
Jonas Maebe
66d4e9a3a5 + dummy int64p.inc 
git-svn-id: trunk@29880 -
 2015-02-23 22:50:51 +00:00
Jonas Maebe
84f04ad2ce + aarch64 fpu rounding mode/exception support 
git-svn-id: trunk@29879 -
 2015-02-23 22:50:48 +00:00