retfq x86 instructions. These are variants of the ret instruction with the
return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
32-bit offset, followed by a 16-bit segment), etc.
git-svn-id: trunk@37571 -
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
with the 186+ 'ins' instruction.
git-svn-id: trunk@37446 -
In comparison with the original patch, support for a i386 has been added as well as a test program.
Further, a small issue with xbegin has been fixed
git-svn-id: trunk@33375 -
using it in inline asm causes an internal error and removing it didn't show
any regressions after running the testsuite on i386-linux.
git-svn-id: trunk@25827 -
* mkx86ins.pp: 'regmem' operand type in x86ins.dat must be converted to OT_RM_GPR, not OT_REGMEM. The latter does not restrict register type, allowing to use e.g. xmm registers in place of regular ones.
* Finished 'movd' and 'movq', added some tests for them to tasm2.pp.
git-svn-id: trunk@17515 -
* Optimized the opcode representation of movq and remaining 3DNow instructions
* Disallow immediates not fitting in 32 bits (Mantis #14685) + test
* Disallow push/pop with 32-bit operands in x86_64 + test
git-svn-id: trunk@17490 -
* Using ot_mmxrm and ot_xmmrm operand types to match arguments, reduces number of required entries by half.
* Replaced all literal $66, $F2 and $F3 prefixes with control codes (\361, \334 and \333, respectively).
* Prefix control codes imply writing REX, so code \323 after them is no longer necessary, removed.
* Fixed technology flags (SSSE3, SSE4.1, SSE4.2)
- Removed codes \300 and \301 (intended to generate address size prefix). FPC does not support this feature (the prefix itself is generated, but process_ea rejects operands needing non-default address size). Probably we don't even need to support it. But if we do, a much simpler solution is check all operands, like today's NASM does.
* Fixed/added some instructions along the way, namely CRC32, UNPCKHPD, CMPNEQSD.
git-svn-id: trunk@17437 -
* Simplified REX handling: instead of useless adjusting instruction length on every REX change, adjust it just once, based on the final REX value.
* Similar for omitting REX.W in certain instructions: set a flag and consider it once the entire instruction has been processed. This removes the requirement for \335 to be the last opcode.
* maybewriterex also after $F2 prefix
* Fixed behavior of codes \310 and \311 (16- and 32-bit address respectively), this is needed for a few fancy instructions like LOOP and JCXZ, which honor address-size prefix instead of REX.
+ control code \361 for $66 prefix
+ IF_SSSE3, IF_SSE41, IF_SSE42 instruction flags (with dummy values)
x86/x86ins.dat:
* replaced literal $67 prefixes with \310 or \311
* marked encodings containing code \310 as NOX86_64
* replaced literal $48 prefixes with \326
git-svn-id: trunk@17433 -
* AESKEYGENASSIST is not ATT-specific name, it is used by Intel-style assemblers as well. Also updated tests/test/taes1.pp to reflect the change.
+ Added SCASQ, resolves#16730 (other opcodes mentioned in that report were added/fixed earlier)
git-svn-id: trunk@17431 -
