+ add methods "call_rtl_mul_const_reg" and "call_rtl_mul_reg_reg" which can call the RTL helpers "fpc_mul_longint" and "fpc_mul_longword" (based on AVR code)
* use the new call methods for the RTL to correctly pass the parameters (on the stack, not in registers...)
git-svn-id: trunk@22892 -
* don't do a sign_extend, but use the correct move size to copy the const; this fixes the setting of the line ending style inside of "Assign"
=> output of strings does now work correctly!
git-svn-id: trunk@22890 -
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
for "CMP" it is important to note that the first operand (which can be basically a register, a constant or a reference) is substracted from the second operand (which needs to be a data register) and not the other way round
git-svn-id: trunk@22798 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
fix the double running of second_pass in the way it was intended to work: check for left.expectloc instead of left.location.loc
git-svn-id: trunk@22788 -
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.
git-svn-id: trunk@22739 -
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).
git-svn-id: trunk@22738 -
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
out code a few lines further down)
git-svn-id: trunk@22736 -
It seems that GNU as needs the syntax "offset(register.size*scale)" if the base address
register is ommited instead of "offset(,register.size*scale)". Now the System unit
assembles and nearly the complete RTL can be built.
git-svn-id: trunk@22734 -
leave "and" and "or" as "and" and "or" as according to the assembly language reference the
assembler should automatically choose the correct instruction (though Coldfire still should
be tested for ORI/ANDI to CCR
git-svn-id: trunk@22733 -
* use andi/ori for constant values
* use a scratch register if target is an address register (there seems to exist an omnious
anda/ora instruction though, but GNU as doesn't seem to handle it... maybe I haven't set
the CPU type correctly, so I'll need to investigate this so we can hopefully remove the
need for a scratch register for certain CPU types ;) )
git-svn-id: trunk@22732 -
* remove comments regarding needed LOC_JUMP implementation
* don't call flags2reg if the location is LOC_JUMP as there isn't a register to set the flags to
(this allows fpc_mul_qword and fpc_mul_int64 to be assembled)
git-svn-id: trunk@22731 -
implement case "LOC_JUMP" (with a more or less blindly copy from
x86/nx86cnv.pas, tx86typeconvnode.second.int_to_bool; this now allows that the system unit can
be compiled, but not yet assembled
git-svn-id: trunk@22728 -
the asmr_d_*_reading messages need an argument which specifies in which style the assembler code
is read; this is most importantly used on i386; on m68k we currently don't have multiple styles,
so simply disable these messages
git-svn-id: trunk@22725 -
like field reordering (possible problems cracker classes) or using ebp as normal register (broken
stack traces from dump_stack)
+ niln is also valid in a cse domain
* parameters passed by reference shall have a complexity >1
* load nodes from outer scopes shall have a complexity >1
* better cse debugging
+ more node types added to cse
* consider parameters passed by reference in cse
* take care of cse in parameters in simple cases
git-svn-id: trunk@22050 -
