1559 Commits

Author	SHA1	Message	Date
J. Gareth "Curious Kit" Moreton	63879e74cd	* x86: Additional TEST/CMP optimisations to optimise CMOV blocks ... that aren't optimal due to register pressure	2024-01-07 14:29:42 +00:00
J. Gareth "Curious Kit" Moreton	47825610b8	* Pass 2 can now be run multiple times when ... under -O3 and above.	2023-11-05 10:03:52 +00:00
J. Gareth "Curious Kit" Moreton	ede47ffea9	* New "fast 3-component LEA hint" and "Icelake" CPU options	2023-10-29 10:26:52 +00:00
florian	99b01f6634	* second mul might get called with a zero operand if the other has a side effect, ... handle this correctly in ti386addnode.second_mul64bit, resolves #40182	2023-03-06 23:19:34 +01:00
J. Gareth "Curious Kit" Moreton	b8933dd267	* x86: Some refactoring to use aoc_ForceNewIteration instead of manually advancing p	2023-03-04 18:40:27 +00:00
J. Gareth "Curious Kit" Moreton	4e8ef448ed	* i386: Bug fix where EBP was marked as preserved when it wasn't, causing faulty optimisations	2023-02-19 16:49:29 +00:00
florian	9c10167b6f	+ CPUX86_HAS_BSWAP	2023-02-04 19:20:10 +01:00
florian	14466ee9d9	* change table updates	2022-12-06 22:41:30 +01:00
florian	8ad7decaa3	* another change information update	2022-12-04 23:17:56 +01:00
florian	42d91c02bd	* continued to fix change information	2022-12-03 23:36:07 +01:00
florian	e0eff8bd89	+ more change information fixed	2022-12-02 23:34:36 +01:00
J. Gareth "Curious Kit" Moreton	170c112301	* x86: Added FMA as an FPU target distinct from AVX and AVX2 (the latter of which has a new FPUX86_HAS_AVX2 flag)	2022-11-25 22:14:59 +00:00
J. Gareth "Curious Kit" Moreton	69c7838571	* x86: Addition of AMD CPUs: Bobcat, Jaguar, Piledriver, Excavator, Zen2 and Zen3 (and supporting flags)	2022-11-25 22:14:59 +00:00
J. Gareth "Curious Kit" Moreton	3cf8ae8433	* x86: New XOR->BTC peephole optimisation	2022-11-15 21:10:47 +00:00
J. Gareth "Curious Kit" Moreton	c9461b7313	* x86: Flags that relate to optimization hints rather than features have been moved to a separate set	2022-11-13 19:23:30 +00:00
J. Gareth "Curious Kit" Moreton	a0c87be0fc	* x86: Zen processors now marked with CPUX86_HAS_FAST_BT_MEM flag	2022-11-12 13:18:53 +00:00
florian	d3abd339b7	+ cpu switch for zen	2022-11-11 23:45:52 +01:00
J. Gareth "Curious Kit" Moreton	aa5517d442	* x86: New CPU feature flags in cpuinfo units	2022-11-11 22:29:58 +00:00
J. Gareth "Curious Kit" Moreton	6757bf3832	* x86: New SHR-based optimisations	2022-09-16 16:57:55 +00:00
J. Gareth "Curious Kit" Moreton	de650dea55	* x86: Fixed minor logic bug in aoc_ForceNewIteration check where UpdateUsedRegs was called at the wrong time.	2022-07-27 16:26:07 +01:00
Jonas Maebe	75c16b6126	llvm: support for getting the llvm rtl (rt) architecture name ... This is the name used as part of the llvm rt libraries, like asan (address sanitizer)	2022-07-24 14:36:13 +02:00
J. Gareth "Curious Kit" Moreton	9432a550e1	* x86: Bug fix where aoc_ForceNewIteration was ... checked in the wrong pass.	2022-07-23 12:58:20 +00:00
florian	f6b5c513bb	* patch by Rika: makes #39786 work on more setups, resolves #39786	2022-07-07 23:00:47 +02:00
Sven/Sarah Barth	7f3a5eb9ab	* extend tabstractprocdef.getcopyas by a parameter to control whether the copy should be registered or not	2022-05-26 21:42:59 +02:00
J. Gareth "Curious Kit" Moreton	6f24c8b4ef	* x86: Code generation fixes where FLAGS ... register is not properly allocated.	2022-04-27 20:46:32 +00:00
J. Gareth "Curious Kit" Moreton	627fb9a25b	* x86: New jump/label tracking in CrossJump optimisations	2022-04-24 16:42:35 +00:00
florian	fab610a927	* call OptPass1_V_MOVAP for MOVDQA on i386	2022-04-19 22:35:02 +02:00
florian	0e4188749b	* started with change information for AVX-512	2022-03-29 22:50:14 +02:00
florian	16881556b9	* change information for AVX-512 mask register instructions	2022-03-28 22:37:09 +02:00
florian	c3ec62878e	* completed change information for AVX-2	2022-03-27 23:06:18 +02:00
florian	6ea0050990	* finished change information for AVX1 instructions	2022-03-26 23:44:59 +01:00
florian	2f33c97006	* more change information	2022-03-25 23:17:57 +01:00
florian	6a56ed24ab	* another change information update	2022-03-24 22:33:27 +01:00
florian	fbf68af605	* continued to update change information	2022-03-23 21:43:08 +01:00
florian	fba3da47c6	* continued to update change information	2022-03-22 22:55:37 +01:00
florian	de98803751	* few more updated change information entries	2022-03-21 22:51:52 +01:00
florian	c785fa4435	* AES instruction change information fixed	2022-03-20 22:32:23 +01:00
florian	2099e35d82	* change information for SSE 4.2 instructions	2022-03-19 23:15:49 +01:00
florian	6421f2c36b	* change information for SSE4.1 instructions	2022-03-18 23:23:31 +01:00
florian	a9db41f1e5	* fixed SSSE3 change information	2022-03-17 22:48:44 +01:00
florian	f5de329076	* change information updates	2022-03-16 23:03:58 +01:00
florian	e9ee0a0be3	* more change information updated	2022-03-15 22:37:49 +01:00
florian	50b6978e68	* more change information updates	2022-03-14 23:11:14 +01:00
florian	b1a72a86e5	* more change information fixed	2022-03-12 22:42:02 +01:00
florian	5e0d5cd92e	* fix change information for a lot of MMX instructions	2022-03-11 22:46:51 +01:00
florian	27fb9086aa	* cleanup: cs_opt_loopunroll is a generic optimization for a long time already	2022-03-08 23:03:18 +01:00
J. Gareth "Curious Kit" Moreton	fe39f9ca21	Fixed bug on x86 platforms where the stack pointer was not allocated if it was different to the frame pointer	2022-02-08 20:47:47 +00:00
J. Gareth "Curious Kit" Moreton	f8e04aad03	CMOV now modifies rather than writes to the destination register so RegUsedAfterInstruction behaves properly	2022-01-28 20:17:24 +00:00
florian	6404478ea4	* cleanup of VER3_0 defines	2021-11-17 22:19:57 +01:00
J. Gareth "Curious Kit" Moreton	2dc0995067	- Bug fix to new ADD/SUB optimisation where conditions are concerned ... - Register allocation fixes for overflow checks	2021-11-17 20:18:57 +00:00