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156 Commits

Author SHA1 Message Date
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888 
git-svn-id: trunk@47103 -
 2020-10-13 19:59:01 +00:00
yury
e5a923eb7a * 8086: Proper implementation of: If a far procvar is called, it must be in a memory location. This fixes a hack to emulate CALL reg1:reg2. 
git-svn-id: trunk@46641 -
 2020-08-23 10:26:54 +00:00
yury
04baeb2bcf * 8086: Reverted r46557. It must be implemented differently. 
git-svn-id: trunk@46561 -
 2020-08-23 00:17:40 +00:00
yury
6a3971c9b6 * 8086: If a far procvar is called, it must be in a memory location. This fixes a hack to emulate CALL reg1:reg2. 
git-svn-id: trunk@46557 -
 2020-08-22 22:12:40 +00:00
yury
97eb32e6fd * 8086: Also fixed loading a register to a 32-bit ref in case the source register is used as the ref base or index. 
git-svn-id: trunk@46491 -
 2020-08-19 10:27:19 +00:00
yury
4873ec73a7 * 8086: Fixed loading a 32-bit ref to a register in case the target register is used as the ref base or index. 
git-svn-id: trunk@46490 -
 2020-08-19 10:20:47 +00:00
yury
0000682043 * i8086: When a ref points to the 32-bit data, preload the ref base to a temp register to reduce spilling. 
git-svn-id: trunk@46204 -
 2020-08-03 18:52:17 +00:00
yury
e70c898503 * Removed the i8086 specific hack. Since r46199 the register allocator is able to handle the problem code. 
git-svn-id: trunk@46200 -
 2020-08-03 16:51:20 +00:00
nickysn
92043c6e20 * call inherited in tcg64f8086.a_op64_reg_ref for OP_NEG and OP_NOT, because it is handled differently after r45302 
git-svn-id: trunk@45305 -
 2020-05-07 11:51:58 +00:00
nickysn
4f4d8191f0 + generate more optimal code for OP_NOT and OP_NEG in tcg64f8086.a_op64_ref 
git-svn-id: trunk@45304 -
 2020-05-07 03:34:20 +00:00
nickysn
52572e10e9 * i8086 compilation fixed after r45302 
git-svn-id: trunk@45303 -
 2020-05-07 02:57:57 +00:00
nickysn
0f6ab0de17 * handle LOC_(C)SUBSETREG/REF in second_NegNot_assign 
* changed the way OP_NEG and OP_NOT are handled in op_reg_ref, in order to be
  consistent with op_reg_reg
* introduced op_reg,op_ref,op_subsetreg,op_subsetref and op_loc for the unary
  operations only (OP_NEG,OP_NOT)

git-svn-id: trunk@45302 -
 2020-05-07 02:43:02 +00:00
florian
11319353fd * loading a got depends only on the fact if a got is needed and not if pic shall be generated 
git-svn-id: trunk@43075 -
 2019-09-25 21:19:06 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
pierre
9c90f593ab Add global range check disable for i8086 cgcpu and x86 nx86add units 
git-svn-id: trunk@40124 -
 2018-10-31 23:20:29 +00:00
florian
d4c65cdac4 * better register de-allocation after CWD/CWB 
git-svn-id: trunk@39413 -
 2018-07-07 21:38:42 +00:00
Jonas Maebe
d69ad8fa41 * removed temppos field again from parameter locations: they're not allocated 
by the temp manager of the current procedure

git-svn-id: trunk@38858 -
 2018-04-27 19:18:55 +00:00
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references, 
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
 2018-04-22 17:03:16 +00:00
nickysn
bd3d35f2da + add support for passing 32-bit values in a pair of registers in 
tcg8086.a_load_const_cgpara. This fixes passing const longint parameters in
  dx:ax when using the register calling convention on i8086.

git-svn-id: trunk@38785 -
 2018-04-18 15:40:09 +00:00
nickysn
4fc2fa7899 * alloc/dealloc NR_DEFAULTFLAGS in the a_cmp_* methods in the i8086 code 
generator

git-svn-id: trunk@37601 -
 2017-11-17 19:28:37 +00:00
nickysn
db09759763 * also integrated the getnextreg() implementation for 8-bit and 16-bit alus from 
the avr and i8086 code generators into the base tcg class

git-svn-id: trunk@37182 -
 2017-09-11 15:47:39 +00:00
nickysn
cf28b202eb * integrated the getintregister() implementation for 8-bit and 16-bit alus from 
the avr and i8086 code generators into the base tcg class (so it can be reused
  by other 8-bit and 16-bit targets)

git-svn-id: trunk@37181 -
 2017-09-11 15:23:59 +00:00
nickysn
ddba821561 * GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved 
from cpubase unit to a method in the tcg class. The reason for doing that is
  that this is now a standard part of the 16-bit and 8-bit code generators and
  moving to the tcg class allows doing extra checks (not done yet, but for
  example, in the future, we can keep track of whether there was an extra
  register allocated with getintregister and halt with an internalerror in case
  GetNextReg() is called for registers, which weren't allocated as a part of a
  sequence, therefore catching a certain class of 8-bit and 16-bit code
  generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
  anything. It might be added to the tcg class, in case it's ever needed, but
  for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.

git-svn-id: trunk@37180 -
 2017-09-11 14:53:06 +00:00
nickysn
4e4e5d6d07 + allocate and free the flags register (when necessary), when generating code 
for OP_SHR,OP_SHL and OP_SAR in tcg64f8086.a_op64_const_reg

git-svn-id: trunk@36021 -
 2017-04-30 01:25:54 +00:00
nickysn
b8c4dd9e18 + implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and 
use it in the shl/shr node for code generation.

git-svn-id: trunk@36018 -
 2017-04-29 21:57:48 +00:00
nickysn
a82c89d894 + implemented OP_SHR,OP_SHL and OP_SAR in a_op64_const_reg for i8086. The shlshr 
node now uses them for 64-bit shift by constant.

git-svn-id: trunk@36017 -
 2017-04-29 20:58:55 +00:00
nickysn
65977f9f27 + implemented OP_ROL and OP_ROR in tcg8086.a_op_reg_reg and .a_op_reg_ref 
git-svn-id: trunk@35952 -
 2017-04-25 13:46:20 +00:00
nickysn
8c200fcfba + implemented OP_SHR,OP_SHL,OP_SAR,OP_ROL and OP_ROR in tcg8086.a_op_const_ref 
git-svn-id: trunk@35945 -
 2017-04-25 11:06:12 +00:00
nickysn
50b1c9c088 + implemented 32-bit OP_SHR,OP_SHL and OP_SAR in tcg8086.a_op_reg_ref 
git-svn-id: trunk@35935 -
 2017-04-24 13:43:18 +00:00
nickysn
7ee0c07b8d + added flags register tracking for many i8086 operations 
git-svn-id: trunk@35848 -
 2017-04-19 13:46:20 +00:00
nickysn
256dc546ac + implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will 
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
  that support performing these operations directly in memory (such as x86)

git-svn-id: trunk@35749 -
 2017-04-07 16:02:40 +00:00
nickysn
9093047a7a * fixed a bug in the i8086 32-bit rol/ror code generation method rm_fast_386 
git-svn-id: trunk@35745 -
 2017-04-06 15:55:43 +00:00
nickysn
1560f20e7f + implemented other 32-bit rol/ror by const methods for i8086 and added a 
(hopefully) reasonable selection for them for all consts between 1 and 31

git-svn-id: trunk@35744 -
 2017-04-06 15:41:39 +00:00
nickysn
0fd860d9e7 * refactored the code generation for 32-bit rol/ror by const for i8086, so it 
uses less code repetition and allow choosing various methods (some of which
  will be implemented later and selected, according to the cpu and optimization
  settings (size vs speed))

git-svn-id: trunk@35743 -
 2017-04-06 13:59:53 +00:00
nickysn
d5e33cce7f * generate better i8086 code for ror32 by 1 and 17 
git-svn-id: trunk@35741 -
 2017-04-05 14:16:00 +00:00
nickysn
321876252b + enabled the rol/ror intrinsic on i8086 
git-svn-id: trunk@35734 -
 2017-04-04 22:37:58 +00:00
nickysn
76cb419241 * use 16-bit 386+ instructions (shld,shrd) for performing fast 32-bit 
shl/shr/sar on i8086, in a_op_const_reg, when the target CPU is set to 80386
  or later

git-svn-id: trunk@35726 -
 2017-04-04 14:40:29 +00:00
nickysn
0ab4f01668 * implemented fast (loopless) 32-bit shift by constant for 8086 as well 
git-svn-id: trunk@35725 -
 2017-04-03 21:04:59 +00:00
nickysn
0f2ad7b712 * generate faster (i.e. loopless) code for 32-bit shl/shr/sar by const on 186+ 
git-svn-id: trunk@35723 -
 2017-04-03 20:37:21 +00:00
nickysn
f0a63fa895 + added an optimized implementation of a_op64_reg_ref for i8086; this improves 
the generated code on i8086 for things like inc(int64_var,int64_var) and
  dec(int64_var,int64_var)

git-svn-id: trunk@35657 -
 2017-03-25 18:45:31 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references 
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
 2016-11-27 18:17:37 +00:00
svenbarth
c8202061dc * get rid of addr_load_indirect again by having tcgx86 provide an internal implementation of both make_simple_ref() and a_load_ref_reg() so that make_direct_ref() can call the latter (and the latter the former) without fear of inifinite recursive calls due to the symbol; a_load_ref_reg() is additionally declared as "final" as a_load_ref_reg_internal() needs to be overloaded instead (which is the case for tcg8086) 
git-svn-id: trunk@34579 -
 2016-09-30 14:01:02 +00:00
Jonas Maebe
aa1be3276f - removed default value of _typ parameter of TAsmData.(Weak)RefAsmSymbol(): 
it was AT_NONE, which is invalid and should never be used
  * explicitly pass the correct value for all calls to those methods elsewhere
    in the compiler

git-svn-id: trunk@34250 -
 2016-08-05 07:09:16 +00:00
nickysn
ac5658470e + use the 16-bit movsx and movzx instructions on 386+ in tcg8086.a_load_ref_reg 
as well

git-svn-id: trunk@34050 -
 2016-07-02 17:05:48 +00:00
nickysn
a5f1ae97d4 + make use of the 16-bit movsx and movzx instructions in tcg8086.a_load_reg_reg 
when the cpu target is 80386 or later

git-svn-id: trunk@34046 -
 2016-07-02 14:06:25 +00:00
nickysn
c78f406d99 + implemented proper stack checking for the i8086 
git-svn-id: trunk@33787 -
 2016-05-24 23:57:47 +00:00
pierre
40193ea1db Add pi_has_open_array_parameter to proc_info.flags as this requires special handling for i8086 huge memory model to restore DS register correctly 
git-svn-id: trunk@32922 -
 2016-01-11 15:02:10 +00:00
Jonas Maebe
d440daf47f * fixed compilation with -Oodfa/-O3 
git-svn-id: trunk@32152 -
 2015-10-25 19:21:57 +00:00
nickysn
09218c88aa + optimizations in tcg8086.g_flags2reg for the case where the carry flag or the 
inverted carry flag is converted to int, using shorter branchless code and
  the adc/rcl/sbb instructions

git-svn-id: trunk@32106 -
 2015-10-20 23:22:32 +00:00
nickysn
b26e10d53c + generate proper win16 prologue/epilogue for exported routines (we don't yet 
actually export them from the .exe or .dll, but they can now be used as
  callbacks)
+ support win16 smart callbacks via the $K switch

git-svn-id: trunk@31835 -
 2015-09-26 18:04:59 +00:00