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11 Commits

Author SHA1 Message Date
Jeppe Johansen
74a7963d58 Redo overflow checking code. 
Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.

git-svn-id: branches/laksen/riscv_new@39762 -
 2018-09-16 18:37:59 +00:00
Jeppe Johansen
1f68caaf82 Removed reuse of src and dest registers in g_concatcopy as that 
could modify registers used for other stuff(ex. framepointer).

git-svn-id: branches/laksen/riscv_new@39717 -
 2018-09-09 14:02:54 +00:00
Jeppe Johansen
90d5f5e760 Added library search paths. 
Removed GP and TP from allocatable registers for now. GP should not be overwritten.
Ported dllprt0.as
Fixed register usage in cprt0.as

git-svn-id: branches/laksen/riscv_new@39522 -
 2018-07-29 13:08:15 +00:00
Jeppe Johansen
27ab039366 Fixed _fini and _init references in cprt0.as 
Add RiscV to fcl-res and fpcres.
Check that constant is a valid imm12 when doing overflow checking.

git-svn-id: branches/laksen/riscv_new@39494 -
 2018-07-23 11:40:55 +00:00
Jeppe Johansen
b98eb3daa9 Changed order in stack unravelling RTL code, to match the most common cases. 
Fixed unsigned conditions for branch conditions.
Added some additional const loading cases.
Changed the temporary register used during calls because it could otherwise clash with the argument passing registers.

git-svn-id: branches/laksen/riscv_new@39492 -
 2018-07-23 01:11:31 +00:00
Jeppe Johansen
2499129ba5 Pass aggregates larger than 2*XLEN as a reference. 
Fix load_reg_reg and make it do proper type conversions.
Added maybeadjust to tcgrv.

git-svn-id: branches/laksen/riscv_new@39485 -
 2018-07-22 14:15:29 +00:00
florian
9776ea2afe * SLTIU -> SLTU 
git-svn-id: branches/laksen/riscv_new@39484 -
 2018-07-22 13:55:53 +00:00
florian
65a415c13e * fix assembling with official binutils 
* fix compilation on 32 bit hosts
+ compile with -Sew

git-svn-id: branches/laksen/riscv_new@39482 -
 2018-07-22 13:10:24 +00:00
Jeppe Johansen
054bf32f1f Add RV64GC cpu type. 
Fix float loading.
Fix a number of small issues with wrong operand sizes.
Fixed concatcopy code generation.
Align jump table for case statements.

git-svn-id: branches/laksen/riscv_new@39481 -
 2018-07-21 22:34:42 +00:00
Jeppe Johansen
768fc2ea4b Added overflow checking in for add instructions. 
git-svn-id: branches/laksen/riscv_new@39479 -
 2018-07-20 15:34:22 +00:00
Jeppe Johansen
ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 
git-svn-id: branches/laksen/riscv_new@39474 -
 2018-07-20 08:21:15 +00:00