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1387 Commits

Author SHA1 Message Date
florian
05ecd784f2 * factored out OptPass1LEA and use it for x86-64 as well 
+ LEAMov2LEA optimization

git-svn-id: trunk@37199 -
 2017-09-13 20:40:32 +00:00
nickysn
ddba821561 * GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved 
from cpubase unit to a method in the tcg class. The reason for doing that is
  that this is now a standard part of the 16-bit and 8-bit code generators and
  moving to the tcg class allows doing extra checks (not done yet, but for
  example, in the future, we can keep track of whether there was an extra
  register allocated with getintregister and halt with an internalerror in case
  GetNextReg() is called for registers, which weren't allocated as a part of a
  sequence, therefore catching a certain class of 8-bit and 16-bit code
  generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
  anything. It might be added to the tcg class, in case it's ever needed, but
  for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.

git-svn-id: trunk@37180 -
 2017-09-11 14:53:06 +00:00
nickysn
30c38a81a9 + also check register type (must be R_INTREGISTER) and subregister (must be 
R_SUBW) in i8086's GetNextReg()

git-svn-id: trunk@37177 -
 2017-09-11 13:25:32 +00:00
nickysn
16d7eefbca + adapted and enabled the x86 specific abs() code generation for i8086, because 
it generates slightly better code, than the generic implementation

git-svn-id: trunk@37161 -
 2017-09-10 12:12:34 +00:00
nickysn
6634141bf4 + generate better code for division by negative power of 2 constants in the x86 
(i386 and x86_64) code generator (same as the division by a positive power of
  2, followed by a NEG instruction, to invert the sign of the result; previously
  the code generator generated an IMUL instruction with a magic constant,
  followed by shift; the new code sequence should be both shorter and faster)

git-svn-id: trunk@37003 -
 2017-08-21 11:35:20 +00:00
florian
dba1761a76 + tcgx86.a_load_reg_ref cuts data if the ref. size is smaller than the reg. size 
git-svn-id: trunk@36953 -
 2017-08-20 16:45:02 +00:00
pierre
6a416a6aa1 use --32/--64 for Darwin GNU assembler calls 
git-svn-id: trunk@36870 -
 2017-08-11 16:04:40 +00:00
pierre
90e846a470 Obsolete system_i386_qnx and remove last references to system_i386_qnx 
git-svn-id: trunk@36860 -
 2017-08-08 18:00:02 +00:00
pierre
c98e9b230f Some watcom assembler wasm improvements 
git-svn-id: trunk@36850 -
 2017-08-04 21:15:10 +00:00
nickysn
19087d04da * replace several emit_const_reg calls that generate SHR or SAR instructions 
with calls to cg.a_op_const_reg in the x86 div code generator, so that the
  same code can be used in the future for i8086 as well (SHR and SAR by
  constants other than 1 are 186+, so on 8086 they have to go through the CL
  register, which is handled correctly in cg.a_op_const_reg)

git-svn-id: trunk@36815 -
 2017-07-31 16:02:52 +00:00
nickysn
9e8cc127b0 * improved the code, generated for signed division by 2 on i386 and x86_64 by 
replacing the sequence
    sar reg, 31 (or 63)
    and reg, 1
  with:
    shr reg, 31 (or 63)

git-svn-id: trunk@36800 -
 2017-07-27 16:02:30 +00:00
nickysn
bb7cd4866d * corrected comment in x86 division code - it said "signed", when it actually meant "negative" 
git-svn-id: trunk@36799 -
 2017-07-27 15:04:56 +00:00
nickysn
b6c3329f20 + also check for negative powers of 2 in the mod by power-of-2 constant x86 optimization, since the sign of the divisor is ignored by the 'mod' operation 
git-svn-id: trunk@36797 -
 2017-07-26 16:10:41 +00:00
nickysn
7c306f18e3 + perform unsigned modulus by power of 2 constant by using an AND instruction (instead of DIV) on x86 
git-svn-id: trunk@36756 -
 2017-07-21 15:58:26 +00:00
florian
22956c4393 + TX86AsmOptimizer.OptPass1OP 
git-svn-id: trunk@36365 -
 2017-05-28 13:49:43 +00:00
florian
c83e6991d5 * properly check number of operands 
git-svn-id: trunk@36322 -
 2017-05-25 12:44:30 +00:00
yury
884cb758e7 * Ensure the number of operands is 2 for MOVXX instructions in OptPass1MOVXX. Otherwise the classic MOVSD/W/B no-operand instructions (REP MOVSX) cause AV during checks of operands. The AV is thrown when trying to compile ucomplex.pp with -Cfsse3. 
* Also fixed generation of debug comments in OptPass1MOVXX.

git-svn-id: trunk@36295 -
 2017-05-22 15:20:18 +00:00
Jonas Maebe
744facb7fc * properly support accepting register parameters of assembler routines in 
the intel assembler reader: no longer parse them as register tokens,
    but as local operands that are later converted into registers. This
    ensures in particular that the type of the operand is set, which is
    necessary in case this operand later subscripted (as in tasm10a)

git-svn-id: trunk@36288 -
 2017-05-21 20:17:15 +00:00
Jonas Maebe
61af0fb72d * only take into account the location of the parameter at the callee side to 
determine whether it's in a register if it's a pure assembler routine
  * you can't "index" implicit pointers either using their fields

git-svn-id: trunk@36287 -
 2017-05-21 20:17:11 +00:00
florian
358bfb4858 * SSE4.1+ implementation of int(...) 
git-svn-id: trunk@36285 -
 2017-05-21 15:28:34 +00:00
florian
3c5ec4e76c * allocate register correctly for "MovMov2Mov 2" 
+ more debug messages
* debug message naming fixed

git-svn-id: trunk@36284 -
 2017-05-21 15:06:22 +00:00
florian
12dec14859 * try to break dependency chains when generating vsqrt instructions 
git-svn-id: trunk@36282 -
 2017-05-21 11:35:33 +00:00
florian
8eec29b139 + enable support for a processor specific frac function 
* implemented inlined frac support for CPUs with SSE4.1+

git-svn-id: trunk@36281 -
 2017-05-21 11:12:59 +00:00
florian
912e6d129a * fix modification flags for *ROUND* 
git-svn-id: trunk@36280 -
 2017-05-21 11:12:57 +00:00
florian
1ffdf02b94 + Ch_*Op4 
+ op_const_reg_reg_reg

git-svn-id: trunk@36279 -
 2017-05-21 11:12:55 +00:00
nickysn
7b70848d83 + allow the src register size to be different from the op size or the dst 
register size for OP_SHR/OP_SHL/OP_SAR/OP_ROL/OP_ROR in tcgx86.a_op_reg_reg().
  This is required for the in_[shr/shl/sar/rol/ror]_assign_x_y inline nodes.

git-svn-id: trunk@36251 -
 2017-05-19 14:03:13 +00:00
florian
0f16f6d94d + OptPass1MOVXX 
git-svn-id: trunk@36209 -
 2017-05-14 20:59:10 +00:00
florian
535c990233 + OptPass1MOVAP 
git-svn-id: trunk@36203 -
 2017-05-13 21:48:44 +00:00
florian
3ade6ae9b8 + Mov2Nop optimization 
git-svn-id: trunk@36201 -
 2017-05-13 09:58:27 +00:00
florian
f4a29bb75d * moved InstructionLoadsFromReg and RegReadByInstruction from TCpuAsmOptimizer (i386) to TX86AsmOptimizer 
git-svn-id: trunk@36200 -
 2017-05-13 09:58:25 +00:00
nickysn
efc5e339d0 * use an enum instead of integer constants to represent inline numbers 
* compinnr.inc include file converted to a unit
* inline number field size stored in ppu increased from byte to longint
* inlines in the parse tree (when written with the -vp option) now printed with
  their enum name, instead of number

git-svn-id: trunk@36174 -
 2017-05-10 14:41:43 +00:00
florian
7b658f56dc * compilation fixed after last cleanup 
git-svn-id: trunk@36166 -
 2017-05-09 20:06:36 +00:00
florian
b1dff29cbf * removed unused units 
git-svn-id: trunk@36165 -
 2017-05-09 19:53:14 +00:00
florian
f93b784895 * make fullcycle for i8086 fixed 
git-svn-id: trunk@36164 -
 2017-05-09 19:53:06 +00:00
florian
52d3756c26 * factored out OptPass1Movx and merged i386 and x86-64 version 
git-svn-id: trunk@36159 -
 2017-05-08 20:44:27 +00:00
florian
06c4c651fd * factored out PrePeepholeOptSxx 
+ x86-64 uses PrePeepholeOptSxx now as well

git-svn-id: trunk@36158 -
 2017-05-08 20:44:24 +00:00
florian
74b338266d * ifdef cmov optimization, as i8086 has no cpu_capabilities 
git-svn-id: trunk@36150 -
 2017-05-07 16:18:44 +00:00
florian
5c2c5d72a2 * use avx for copying data only on i386 for 8 byte chunks 
git-svn-id: trunk@36149 -
 2017-05-07 16:18:42 +00:00
florian
f8d517be70 * make TX86AsmOptimizer.IsExitCode usable for x86-64 as well 
git-svn-id: trunk@36148 -
 2017-05-07 16:18:40 +00:00
florian
4a43d992f5 * unified usage of MatchOpType 
* fixed generic MatchOpType

git-svn-id: trunk@36145 -
 2017-05-07 16:18:33 +00:00
florian
7afe762d22 * factored out OptPass2Jcc assembler optimization 
* OptPass2Jcc now used by x86-64 as well
* remove orphaned alignments if the label is not used anymore after cmov is used

git-svn-id: trunk@36143 -
 2017-05-07 12:45:48 +00:00
florian
e3f0b338d4 * SkipLabels moved to aoptutils 
* factored out OptPass2Jmp assembler optimization
* OptPass2Jmp now used by x86-64 as well

git-svn-id: trunk@36141 -
 2017-05-06 21:07:02 +00:00
florian
f985971a62 * apply mov reg1, mem1; cmp x, mem1 to mov reg1, mem1; cmp x, reg1 also for test 
git-svn-id: trunk@36138 -
 2017-05-06 18:47:47 +00:00
nickysn
c28d533bb0 + support the cmpsd sse instruction in the at&t inline assembly reader 
git-svn-id: trunk@36124 -
 2017-05-05 15:46:47 +00:00
nickysn
98d2684368 + correctly support the sse2 version of the cmpsd x86 instruction, when writing 
at&t style asm output

git-svn-id: trunk@36122 -
 2017-05-05 15:01:38 +00:00
nickysn
b882ba5fd2 + also recognize sbb reg,reg as writing a new value in the register in TX86AsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@36119 -
 2017-05-05 14:24:13 +00:00
nickysn
af48d176ec + precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions 
git-svn-id: trunk@36115 -
 2017-05-05 13:41:43 +00:00
nickysn
0e0e5c0caf + support the flags register and its subregisters in TX86AsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@36114 -
 2017-05-05 12:17:50 +00:00
nickysn
85fbbec319 + recognize xor reg,reg (same register twice) and sub reg,reg as writing a new 
value to reg in TX86AsmOptimizer.RegLoadedWithNewValue

git-svn-id: trunk@36112 -
 2017-05-05 11:01:34 +00:00
nickysn
aa93259463 + support the lahf,fstsw and fnstsw instructions in 
TX86AsmOptimizer.RegLoadedWithNewValue

git-svn-id: trunk@36087 -
 2017-05-04 16:02:01 +00:00