379 Commits

Author	SHA1	Message	Date
florian	657f3c52bf	* according to Jonas iOS doesn't zero extend results in the callee either, so check removed	2023-09-12 23:05:48 +02:00
florian	a517ada539	* on aarch64-darwin, the unused part of function results is not cleared	2023-09-10 19:27:21 +02:00
Pierre Muller	5a123d33ba	Add -Awin64-as option for aarch64 compiler for win64 target	2023-05-26 11:15:55 +00:00
Dmytro Bogatskyy	327aac7f24	Add aarch64-iphonesim target	2023-03-27 18:45:00 +00:00
florian	dfb8794d4d	* compilation after merge fixed	2023-01-25 20:44:34 +01:00
Pierre Muller	aaa6f0d9c5	Only signed extension is needed	2023-01-25 19:36:45 +00:00
Pierre Muller	4793447be1	Add sign extension to 32-bit for unaligned OS_8 and OS_16 types (to try to solve #40102)	2023-01-25 19:36:45 +00:00
Pierre Muller	cd8aa3f0e0	Avoid generation of invalid 'cb(n)z sp,label' instruction	2023-01-02 18:22:49 +00:00
florian	4430422489	* improve module local data accesses by avoiding a got read	2022-12-28 22:05:23 +01:00
Jonas Maebe	851af5033f	Darwin/AArch64: adjust alignment info of custom-aligned paralocs ... Resolves #40019	2022-12-06 21:46:26 +01:00
Jonas Maebe	230142e183	AArch64 cgcpu: add missing brackets around and/or expression	2022-12-03 21:17:18 +01:00
Jonas Maebe	cd8ddffe42	AArch64: X18 is not a volatile register ... It may be unused on some platforms, but in general it's reserved for OS library usage (usually related to TLS)	2022-10-29 14:24:37 +02:00
florian	3a11ee9a14	* apply OptPass1Data to neg as well	2022-09-06 21:42:29 +02:00
florian	5cbb36f218	* factor out TARMAsmOptimizer.USxtOp2Op	2022-09-03 19:21:28 +02:00
florian	ed7b0c5e68	* AArch64: extended SxtwMov2Data to CMP and CMN	2022-09-03 19:03:48 +02:00
florian	ad1c19864d	* small refactoring	2022-09-01 21:44:18 +02:00
florian	9adcc891cf	+ Aarch64: SxtwOp2Op optimization	2022-09-01 21:44:18 +02:00
florian	29495c9ba5	* refactor TCpuAsmOptimizer.OptPass1SXTW	2022-09-01 21:44:18 +02:00
florian	fd94b6db91	* fix for TCpuAsmOptimizer.OptPass1SXTW	2022-08-31 20:43:49 +02:00
florian	8a0498622b	+ AArchz64: TCpuAsmOptimizer.OptPass1SXTW	2022-08-31 20:33:59 +02:00
florian	5a60eac0c8	+ MovzMovz2Movz optimization	2022-08-29 21:36:14 +02:00
florian	ceab50cafb	* use simpler FMOV instead of UMOV	2022-08-03 22:42:25 +02:00
J. Gareth "Curious Kit" Moreton	d6ff4ed967	* arm/a64: New sbfx/ubfx -> mov optimisation	2022-07-30 18:36:16 +00:00
J. Gareth "Curious Kit" Moreton	637645b6d6	* a64: New movz reg,#0 -> mov reg,xzr (or wzr) optimisation	2022-07-30 18:36:16 +00:00
Robert Roland	7cefe8a822	Adding AArch64 CurrentEL register ... CurrentEL is used to determine the current "exception level" in the CPU. It has four possible results: 0b00 - EL0 - Application 0b01 - EL1 - Rich OS 0b10 - EL2 - Hypervisor 0b11 - EL3 - Firmware https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/CurrentEL--Current-Exception-Level https://developer.arm.com/documentation/102412/0100/Privilege-and-Exception-levels	2022-07-25 19:05:00 +00:00
Robert Roland	a19add9c88	Add cntfrq_el0 and cntpct_el0 AArch64 registers	2022-07-05 20:40:27 +00:00
florian	81fd3e2748	* more readable fix for the missing ait_instruction check	2022-05-15 19:32:27 +02:00
J. Gareth "Curious Kit" Moreton	27db63969a	* a64: Fix where hp1's was assumed to be an instruction and not actually checked	2022-05-15 16:47:55 +00:00
florian	e8da1d081a	+ Aarch64: MovOp2AddUtxw optimization	2022-05-14 22:30:56 +02:00
Jonas Maebe	9813eb9048	AArch64 asm reader: add support for fpcmp(e) conditions ... Resolves #39643	2022-04-03 13:40:21 +02:00
florian	27fb9086aa	* cleanup: cs_opt_loopunroll is a generic optimization for a long time already	2022-03-08 23:03:18 +01:00
Robert Roland	fbc65314b9	Correct linker script for aarch64-embedded ... Start address was wrong, should be 0x80000, not 0x8000	2022-01-22 22:28:38 +01:00
florian	a362c93f73	* Aarch64: operations affect always the full 64 bit register, so ... TCpuAsmOptimizer.RegLoadedWithNewValue can use SuperRegistersEq	2022-01-20 22:15:14 +01:00
Robert Roland	86c097086a	Additional copyright header	2022-01-05 12:29:00 +00:00
Robert Roland	53e5a4a03a	Adding aaarch64-embedded target ... This adds support for aarch64-embedded, specifically for the Raspberry Pi 3. Uses UART0 at 115200 baud 8N1 for console IO.	2022-01-05 12:29:00 +00:00
florian	e443936e12	+ in_min/max_dword/longint support for aarch64	2021-12-19 16:16:44 +01:00
florian	77b9d62520	+ in_min/max_single/double support for aarch64	2021-12-18 21:23:21 +01:00
florian	b733e21fd1	+ more AArch64 extensions	2021-11-20 20:47:47 +01:00
florian	67f3a7502d	+ Aaarch64: support adr instructions with local labels in the assembler reader ... + throw an error if an illegal instruction extension is passed as command line option	2021-11-19 22:37:47 +01:00
florian	6404478ea4	* cleanup of VER3_0 defines	2021-11-17 22:19:57 +01:00
florian	d708bef92f	+ Aarch64: read register sets with ranges properly ... + tests	2021-11-07 20:02:29 +01:00
florian	f570b6cb7b	+ more Aarch64 cpu capability flags added	2021-11-07 11:06:01 +01:00
florian	c1d43df4a1	+ be able to add single cpu capabilites by the command line ... + AArch64: SHA2 capability	2021-11-06 23:32:56 +01:00
florian	716e8c8e89	* tcgsizep2size now supports all tcgsize values	2021-11-06 21:16:07 +01:00
Florian Klämpfl	a47f153dae	* avoid to create a stack frame on aarch64 if possible	2021-11-02 22:23:24 +01:00
florian	e0a78c2485	* tcgaarch64.g_concatcopy calls tcgaarch64.g_concatcopy_move only if the current subroutine has pi_do_call set ... * fixed copy loop in tcgaarch64.g_concatcopy if ldp/stp is used: fixed increment calculation and fixed tail length calculation	2021-11-02 22:01:52 +01:00
florian	fcdbb31ec4	* AArch64: TCpuAsmOptimizer.RegLoadedWithNewValue: check if p.ops=0	2021-11-01 11:46:19 +01:00
florian	ff3acfb8cd	* cleanup of 2.7.0 defines	2021-10-31 13:20:28 +01:00
florian	fb7cdbefb3	+ some opcodes added	2021-10-30 20:21:59 +02:00
Pierre Muller	7778d20003	Avoid range check error in TCpuAsmOptimizer.OptPostAnd method	2021-10-04 21:08:24 +00:00