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58 Commits

Author SHA1 Message Date
florian
746bfced25 Synchronized with trunk, part 1 (only make cycle tested, make all is broken, avx-512 support not yet tested 
git-svn-id: branches/tg74/avx512@42642 -
 2019-08-10 13:53:20 +00:00
florian
4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 
+ avxopcodes tests also movbe and pclmulqdq

git-svn-id: trunk@40951 -
 2019-01-20 18:50:12 +00:00
tg74
1ef9cc01e6 avx512 disp8*N 
git-svn-id: branches/tg74/avx512@39909 -
 2018-10-09 21:19:52 +00:00
florian
8943c0584e + patch by J. Gareth Moreton to support BMI2 instructions 
+ extended avx test generator with the newly added BMI2 instructions

git-svn-id: trunk@39875 -
 2018-10-07 10:10:19 +00:00
tg74
fba72b280b avx512 broadcast vcvt...,vfpclass... 
git-svn-id: branches/tg74/avx512@39778 -
 2018-09-19 15:28:15 +00:00
tg74
dd967ecfee remove any gather/scatter opcodes for nights mill 
git-svn-id: branches/tg74/avx512@39742 -
 2018-09-12 09:59:04 +00:00
tg74
608992ecf5 minor bugfixes avx512 tests 
git-svn-id: branches/tg74/avx512@39740 -
 2018-09-12 05:03:05 +00:00
tg74
c611e4814a new avx512 opcodes 
git-svn-id: branches/tg74/avx512@39720 -
 2018-09-10 06:19:45 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes 
git-svn-id: branches/tg74/avx512@39705 -
 2018-09-03 05:40:44 +00:00
tg74
914e31dbd1 new AVX512 instructions vextracti..,vextractf.. 
git-svn-id: branches/tg74/avx512@39674 -
 2018-08-27 06:06:27 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512 
git-svn-id: branches/tg74/avx512@39636 -
 2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register 
git-svn-id: branches/tg74/avx512@39457 -
 2018-07-16 17:06:57 +00:00
tg74
31e4d4ef5e AVX512 support for MMRegister xmm16..31 and ymm16..31, zmm0..31, vpaddsb support AVX512 
git-svn-id: branches/tg74/avx512@39196 -
 2018-06-08 06:53:35 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd. 
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
 2018-03-03 23:32:54 +00:00
marco
f21a141144 * mantis #32001, add 32 vcmpps variants. 
git-svn-id: trunk@38403 -
 2018-03-03 23:10:03 +00:00
nickysn
ae92973196 + added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and 
retfq x86 instructions. These are variants of the ret instruction with the
  return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
  a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
  32-bit offset, followed by a 16-bit segment), etc.

git-svn-id: trunk@37571 -
 2017-11-10 16:53:29 +00:00
nickysn
e8bbc4eef9 + support the xlat x86 instruction syntax with a memory operand. This allows 
specifying the address size (e.g. xlat byte ptr [bx] or xlat byte ptr [ebx])

git-svn-id: trunk@37478 -
 2017-10-17 16:40:06 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions 
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
 2017-10-12 00:07:02 +00:00
sergei
133fcb5ab2 * Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code. 
+ Test

git-svn-id: trunk@34949 -
 2016-11-21 13:59:44 +00:00
sergei
ebe134febc * Fixed memory reference size for MOVSS instruction, Mantis #29954. 
git-svn-id: trunk@34943 -
 2016-11-21 03:31:25 +00:00
sergei
870fda34d5 * x86 AT&T reader and writer: cleaned up usage of attsufMM suffix: 
* It is now only used to select size of vector instructions (i.e. 128 or 256 bits)
  * Scalar instructions reverted to use attsufINT suffix (selecting between 32 or 64 bits).
  * Additionally, vcvtsi2sd and vcvtsi2ss with rm64 operand are x86_64 only.

git-svn-id: trunk@34942 -
 2016-11-21 02:07:13 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933 
git-svn-id: trunk@34917 -
 2016-11-18 20:19:39 +00:00
florian
406e3c4ac1 + support xgetbv instruction, resolves issue #29958 
git-svn-id: trunk@33418 -
 2016-04-03 20:53:10 +00:00
florian
8d5cc3dfa4 * (extended and modified) patch by Emelyanov Roman to add suport of RDRAND, RDSEED and TSX instructions set, resolves issue #29893. 
In comparison with the original patch, support for a i386 has been added as well as a test program. 
  Further, a small issue with xbegin has been fixed

git-svn-id: trunk@33375 -
 2016-03-28 19:08:13 +00:00
florian
a3964d9ee0 + support for RDTSCP, resolves issue #28916 
git-svn-id: trunk@32652 -
 2015-12-13 13:28:51 +00:00
florian
d6e4af8279 + applied remaining patches of Torsten Grundke: adds gather instructions of avx2 
git-svn-id: trunk@29745 -
 2015-02-17 21:43:46 +00:00
florian
842e027a9f + prove of concept how FMA4 could be supported in inline assembler 
git-svn-id: trunk@27214 -
 2014-03-20 21:25:38 +00:00
florian
a79be2b05c + support for FMA instructions in inline assembler 
+ extended avx test code with FMA

git-svn-id: trunk@27209 -
 2014-03-20 20:06:56 +00:00
florian
aa107b914c * merged avx2 branch, developed by Torsten Grundke 
git-svn-id: trunk@27200 -
 2014-03-20 12:03:52 +00:00
florian
7028210817 + tzcnt assembler instruction 
git-svn-id: trunk@26506 -
 2014-01-18 12:11:50 +00:00
nickysn
0f69362edd - rm LEA reg,imm from x86ins.dat, as that's not a valid x86 instruction, 
using it in inline asm causes an internal error and removing it didn't show
  any regressions after running the testsuite on i386-linux.

git-svn-id: trunk@25827 -
 2013-10-18 23:26:58 +00:00
florian
9b6094a58c + added a few BMI instructions to see if they can be encoded 
git-svn-id: trunk@24907 -
 2013-06-16 09:35:21 +00:00
florian
283ff05127 * merged avx support in inline assembler developed by Torsten Grundke 
git-svn-id: trunk@22568 -
 2012-10-06 19:47:18 +00:00
florian
fc569e224d * handle all operand combinations of xadd, resolves #21146 
git-svn-id: trunk@20177 -
 2012-01-25 21:26:59 +00:00
florian
8308b46a94 + support for assembler instructions with four operands 
+ support for insertq, resolves #19910

git-svn-id: trunk@18206 -
 2011-08-14 16:46:35 +00:00
sergei
0231863fce + Added missing PMULLD instruction, part of Mantis #19910 
git-svn-id: trunk@18106 -
 2011-08-06 06:59:33 +00:00
sergei
354d0520b7 + x86 assembler: fixed MOVABS instruction (it is a x86_64-only subset of MOV with 8-byte immediates/offsets) and same-form encodings of MOV instruction. 
git-svn-id: trunk@17666 -
 2011-06-05 17:32:18 +00:00
sergei
504e0c6816 x86 assembler fixes: 
* mkx86ins.pp: 'regmem' operand type in x86ins.dat must be converted to OT_RM_GPR, not OT_REGMEM. The latter does not restrict register type, allowing to use e.g. xmm registers in place of regular ones. 
* Finished 'movd' and 'movq', added some tests for them to tasm2.pp.

git-svn-id: trunk@17515 -
 2011-05-20 20:39:35 +00:00
sergei
9e8a31193b x86 assembler: 
* Optimized the opcode representation of movq and remaining 3DNow instructions
* Disallow immediates not fitting in 32 bits (Mantis #14685) + test
* Disallow push/pop with 32-bit operands in x86_64 + test

git-svn-id: trunk@17490 -
 2011-05-17 20:06:12 +00:00
sergei
3b979fef6d * Re-commit r17437 after more testing and fixing aasmcpu.pp in r17449. 
git-svn-id: trunk@17452 -
 2011-05-14 11:04:52 +00:00
sergei
b257231203 * Revert r17437, it breaks builds with -O2 and builds on i386 (although -O- on x86_64 is ok). 
git-svn-id: trunk@17439 -
 2011-05-12 23:53:18 +00:00
sergei
1d81a1244b A big update of x86 instruction table, part 1 (mostly SIMD instructions): 
* Using ot_mmxrm and ot_xmmrm operand types to match arguments, reduces number of required entries by half.
* Replaced all literal $66, $F2 and $F3 prefixes with control codes (\361, \334 and \333, respectively).
* Prefix control codes imply writing REX, so code \323 after them is no longer necessary, removed.
* Fixed technology flags (SSSE3, SSE4.1, SSE4.2)
- Removed codes \300 and \301 (intended to generate address size prefix). FPC does not support this feature (the prefix itself is generated, but process_ea rejects operands needing non-default address size). Probably we don't even need to support it. But if we do, a much simpler solution is check all operands, like today's NASM does.
* Fixed/added some instructions along the way, namely CRC32, UNPCKHPD, CMPNEQSD.

git-svn-id: trunk@17437 -
 2011-05-12 19:49:19 +00:00
florian
9279c6955e * support for SSSE3, SSE4,1, SSE4.2, AES instructions set by Emelyanov Roman, resolves #18527 
+ test for aes support

git-svn-id: trunk@17256 -
 2011-04-05 20:22:57 +00:00
florian
49195b0ac0 * fixes assembling of mov ax,<mem16> 
* fixes assembling of test <mem8>,reg8; resolves #11786

git-svn-id: trunk@12040 -
 2008-11-09 10:24:59 +00:00
florian
447276c5bb * Jcc reads the flags, this was not in the dat yet, resolves #9278 
* disabled 4 ops variant of insertq for now

git-svn-id: trunk@8133 -
 2007-07-22 16:40:44 +00:00
florian
0e96eda236 + some sse4 instructions supported, resolves #9046 
git-svn-id: trunk@7613 -
 2007-06-09 19:45:06 +00:00
florian
6118c3e477 * fixed assembling of movd with 64 bit registers 
* fixed passing of floats to c varargs

git-svn-id: trunk@5477 -
 2006-11-25 20:32:32 +00:00
peter
d79df4c74a * 64bit support for shrd 
git-svn-id: trunk@4541 -
 2006-09-03 08:56:10 +00:00
peter
eb725d4e44 Merged revisions 2908,2911,2913-2917 via svnmerge from 
http://svn.freepascal.org/svn/fpc/branches/linker/compiler

........
r2908 | peter | 2006-03-13 13:35:48 +0100 (Mon, 13 Mar 2006) | 2 lines

  * merge trunk upto r2907

........
r2911 | peter | 2006-03-13 18:08:00 +0100 (Mon, 13 Mar 2006) | 2 lines

  * rename values to make room for operand size codes

........
........
........
r2915 | peter | 2006-03-14 13:51:35 +0100 (Tue, 14 Mar 2006) | 2 lines

  * check aktcputype

........
r2916 | peter | 2006-03-14 15:06:32 +0100 (Tue, 14 Mar 2006) | 3 lines

  * merge 300 opcodes
  * more 64bit versions of opcodes

........
r2917 | peter | 2006-03-14 17:34:03 +0100 (Tue, 14 Mar 2006) | 3 lines

  * x86_64 tables
  * convert movq with normal registers to mov

........

git-svn-id: trunk@2931 -
 2006-03-16 08:09:28 +00:00
florian
5ece7cbc2f * first part of x86-64 assembler 
git-svn-id: trunk@2824 -
 2006-03-09 22:05:16 +00:00