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a018235811
Commit Graph

20129 Commits

Author SHA1 Message Date
nickysn
a018235811 * fixed powerpc compiler compilation with -dEXTDEBUG 
git-svn-id: trunk@35982 -
 2017-04-27 17:25:33 +00:00
nickysn
ff1ee6836d + fix RegReadByInstruction for the x86 MOVSD instruction 
git-svn-id: trunk@35968 -
 2017-04-27 14:42:08 +00:00
nickysn
7ea0429d40 + added new compiler debug ifdef DEBUG_INSTRUCTIONREGISTERDEPENDENCIES, which 
adds instruction register usage info to the assembly output (only register
  reads for now, but register writes will also be added later). Useful for
  debugging InstructionLoadsFromReg and other similar functions.

git-svn-id: trunk@35967 -
 2017-04-27 13:40:58 +00:00
nickysn
b741e38f98 + precise handling for x86 conditions and their flag bits in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@35965 -
 2017-04-27 12:07:48 +00:00
nickysn
8512f8240e + enable constant propagation across 2-parameter inc()/dec() calls 
git-svn-id: trunk@35962 -
 2017-04-26 23:21:44 +00:00
nickysn
012153201a * moved the conversion of "x:=x op k" to inline nodes to a separate optimization 
pass, so that it can be done after other optimizations, such as constant
  propagation

git-svn-id: trunk@35961 -
 2017-04-26 22:44:01 +00:00
Jonas Maebe
aa82e00615 * fixed check to determine whether a record parameter can be subscripted 
directly in inline assembly: that's only possible if it's a register
    parameter where the address of the record was passed (rather than the
    record itself), or if a parameter has been explicitly typecasted in
    Intel-style assembly using ".size"

git-svn-id: trunk@35959 -
 2017-04-26 19:43:35 +00:00
nickysn
0f010430cc + better precision in determining the registers, read by mul/imul/div/idiv in 
i386's TCpuAsmOptimizer.RegReadByInstruction:
  * mul doesn't read edx (unless included in operand)
  * 8-bit mul and imul don't read ah (unless included in operand)
  * 8-bit div and idiv don't read edx (unless included in operand)

git-svn-id: trunk@35958 -
 2017-04-26 16:17:31 +00:00
nickysn
916c09af55 + also check the register type when checking for specific integer registers in 
i386's TCpuAsmOptimizer.RegReadByInstruction. Previously, the lack of this
  check could generate false reads on some other register types (e.g. mmx/xmm/
  flags, etc.), and this could worsen optimizations.

git-svn-id: trunk@35957 -
 2017-04-26 15:25:38 +00:00
nickysn
618b6292ee + support testing for individual bits from the x86 flags register in i386's 
TCpuAsmOptimizer.RegReadByInstruction()

git-svn-id: trunk@35956 -
 2017-04-26 14:38:36 +00:00
nickysn
c8487c4150 + added individual bits of the x86 flags register as subregisters 
git-svn-id: trunk@35955 -
 2017-04-26 13:52:52 +00:00
nickysn
5f66f5cebb + distinguish between x86 flags subregisters: flags, eflags and rflags 
git-svn-id: trunk@35953 -
 2017-04-25 16:10:43 +00:00
nickysn
65977f9f27 + implemented OP_ROL and OP_ROR in tcg8086.a_op_reg_reg and .a_op_reg_ref 
git-svn-id: trunk@35952 -
 2017-04-25 13:46:20 +00:00
nickysn
8c200fcfba + implemented OP_SHR,OP_SHL,OP_SAR,OP_ROL and OP_ROR in tcg8086.a_op_const_ref 
git-svn-id: trunk@35945 -
 2017-04-25 11:06:12 +00:00
nickysn
5393daa994 + added compile time const evaluation for Bsf/Bsr(const) as well 
git-svn-id: trunk@35941 -
 2017-04-24 20:35:08 +00:00
nickysn
32395bbcbb + added compile time const evaluation optimization for PopCnt(const) 
git-svn-id: trunk@35937 -
 2017-04-24 16:11:43 +00:00
nickysn
9a1812dfd9 + optimize OP_XOR by 0 to OP_NONE in optimize_op_const 
git-svn-id: trunk@35936 -
 2017-04-24 14:26:33 +00:00
nickysn
50b1c9c088 + implemented 32-bit OP_SHR,OP_SHL and OP_SAR in tcg8086.a_op_reg_ref 
git-svn-id: trunk@35935 -
 2017-04-24 13:43:18 +00:00
pierre
d6bf9e03ec Add missing management operator options to ppudump 
git-svn-id: trunk@35934 -
 2017-04-24 12:43:30 +00:00
nickysn
0c244046a9 * proper register change info for the movs,cmps and scas x86 string instructions 
(movsd still todo, because of the overlap with the sse2 instruction)

git-svn-id: trunk@35929 -
 2017-04-23 21:30:25 +00:00
sergei
5165497498 * MIPS: fixed TCpuAsmOptimizer.InstructionLoadsFromReg, it now correctly considers instructions that read their first operand. 
git-svn-id: trunk@35921 -
 2017-04-23 15:26:17 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read 
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
 2017-04-22 22:07:05 +00:00
florian
4868b83157 * do not generate always debug messages in the arm assembler optimizer 
git-svn-id: trunk@35891 -
 2017-04-22 09:37:18 +00:00
florian
6af656aaed + DebugMsg based debugging for the mips(el) assembler optimizer 
git-svn-id: trunk@35890 -
 2017-04-22 09:36:44 +00:00
pierre
6eee90ad3f Fix section alignment code for GNU assembler for smartlinked objects on aix system 
git-svn-id: trunk@35885 -
 2017-04-22 08:48:23 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86 
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
 2017-04-21 23:03:33 +00:00
florian
50dba9ad66 * if both labels of a case label are equal, we still cannot skip the comparison in a jump tree, resolves #31589 
git-svn-id: trunk@35880 -
 2017-04-21 19:32:27 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read 
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
 2017-04-20 15:11:56 +00:00
nickysn
328d546155 + extend the i8086 peephole optimization that converts certain sequences to lds 
and les instructions to also support the lss, lfs and lgs instructions on i386
  (won't be generated by the current code generator, but might become useful in
  the future, if we start using the fs and gs segment registers as well)

git-svn-id: trunk@35858 -
 2017-04-20 13:00:26 +00:00
nickysn
ec11864272 * use a native sized int register for the shift count in in_sar_assign_x_y, 
in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y

git-svn-id: trunk@35857 -
 2017-04-20 12:38:54 +00:00
nickysn
af235cae86 * use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr 
sequence on i386

git-svn-id: trunk@35856 -
 2017-04-19 21:30:31 +00:00
nickysn
12a1ad66b2 + added the Ch_RDirFlag change attribute to the STOSx instructions (previously 
was missing, due to the 3 attributes per instruction limit)

git-svn-id: trunk@35855 -
 2017-04-19 20:23:24 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set; 
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
 2017-04-19 16:48:35 +00:00
nickysn
189e49998c * fixes to the x86 instruction flags tracking attributes: 
* AAA and AAS also read flags (AF)
  * CMC reads and writes flags (it inverts CF)
  * CMPSx and SCASx write flags
  * CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
  * NOT doesn't affect flags
  * REP isn't affected by and doesn't affect flags
  * REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
  * ROL and ROR don't read flags
  * SAL doesn't read flags
  * SHLD and SHRD don't read flags

git-svn-id: trunk@35849 -
 2017-04-19 15:42:50 +00:00
nickysn
7ee0c07b8d + added flags register tracking for many i8086 operations 
git-svn-id: trunk@35848 -
 2017-04-19 13:46:20 +00:00
nickysn
e708a76f70 * some i386 optimizations for 64-bit SHL/SHR/SAR in tcg64f386.a_op64_const_reg: 
* only use SHx/RCx when optimizing for size
  * use ADD reglo,reglo + ADC reghi,reghi for SHL by 1 on i386 and i486

git-svn-id: trunk@35841 -
 2017-04-18 21:30:31 +00:00
nickysn
0264c4cace + implemented OP_SHR/OP_SHL/OP_SAR correctly in tcg64f386.a_op64_const_ref for 
const values larger than 31

git-svn-id: trunk@35838 -
 2017-04-18 16:02:48 +00:00
nickysn
16af6f03fb + support OP_SHR/OP_SHL/OP_SAR/OP_ROL/OP_ROR in tcgx86.a_op_reg_ref 
git-svn-id: trunk@35837 -
 2017-04-18 15:14:28 +00:00
nickysn
d7b8d8dd54 * don't emit the "SUB ECX,32" instruction on i386, when doing a 64-bit shift by 
reg, with a value >=32. The instruction is redundant, because the SHL/SHR
  instructions already AND mask the shift count by 31.

git-svn-id: trunk@35836 -
 2017-04-18 15:09:20 +00:00
nickysn
d7c8a081a1 + enable using the cg64 ops OP_SHR/OP_SHL/OP_SAR on i386 for implementing the 
64-bit in_sar/shl/shr_assign_x_y inline nodes

git-svn-id: trunk@35835 -
 2017-04-18 14:36:41 +00:00
nickysn
03dfa07ebc + implemented OP_SHR/OP_SHL/OP_SAR in i386's tcg64f386.a_op64_reg_ref 
git-svn-id: trunk@35834 -
 2017-04-18 14:34:20 +00:00
pierre
17b2671213 Regenerate all Makefile's after changes related to FPCDIR checks 
git-svn-id: trunk@35833 -
 2017-04-18 14:15:47 +00:00
nickysn
3d28878210 + added taicpu.op_reg_reg_ref() constructor for x86, in order to support the 
shld/shrd [ref],reg,CL instructions

git-svn-id: trunk@35832 -
 2017-04-18 12:47:57 +00:00
nickysn
10d7603dce + implemented OP_SHR/OP_SHL/OP_SAR support in tcg64f386.a_op64_reg_reg 
git-svn-id: trunk@35831 -
 2017-04-18 12:24:46 +00:00
nickysn
7e8c89435f * avoid the AND instruction in the i386 shr64/shl64 code, by using TEST+JZ, 
instead of CMP+JL

git-svn-id: trunk@35830 -
 2017-04-18 11:36:48 +00:00
Jonas Maebe
4e1f999b02 * write full path name when ppu crc checks fail/conflict (patch by 
C. Western, mantis #31650)

git-svn-id: trunk@35823 -
 2017-04-17 20:42:03 +00:00
nickysn
b14f277e8f + use rtl helpers for 64-bit shl/shr/sar/rol/ror modify in place operations, on 
platforms that don't have native 64-bit implementation of the corresponding
  64-bit shift/rotate operation

git-svn-id: trunk@35787 -
 2017-04-13 15:24:32 +00:00
nickysn
a1ad705646 + allocate and free flags before and after the shl+rcl/shr+rcr/sar+rcr sequences 
git-svn-id: trunk@35786 -
 2017-04-13 11:58:51 +00:00
nickysn
cddb48bad4 + i386 implementation of a_op64_const_reg for OP_SHR,OP_SHL and OP_SAR; needed 
by the in_shl/shr/sar_assign_x_y inline nodes

git-svn-id: trunk@35785 -
 2017-04-13 11:54:19 +00:00
nickysn
6a710964f2 + i386 implementation of a_op64_const_ref for OP_SHR,OP_SHL and OP_SAR; needed 
by the in_shl/shr/sar_assign_x_y inline nodes

git-svn-id: trunk@35784 -
 2017-04-13 10:38:33 +00:00