and getters for the ttemp*node classes instead
o this will allow descendants to prevent certain flags from being added
or removed. E.g. for LLVM, certain temps must never be put in registers
because it cannot typecast a value in a register from a non-record/array
type to an array type without forcing it to memory (so if that is done
on an lvalue, the result will be written to the memory temp instead of
to the register)
git-svn-id: trunk@34358 -
tasmdata.DefineAsmSymbol() and all routines that call it
o will be used to automatically generate AB_INDIRECT sybols when
necessary
git-svn-id: trunk@34164 -
initialloc was already set afterwards, now it's also done in the final
case (and allocating the initial location should be different from
setting the current location)
git-svn-id: trunk@34085 -
Merged revision(s) 28793, 28903, 31951 from branches/svenbarth/packages:
psub.pas, read_proc:
* don't generate assembler symbols for compiler internal code
........
Ensure that unneeded initialization/finalization procedures don't leave assembler symbols.
ncgutil.pas:
+ new function release_proc_symbol which removes all assembler symbols of a procdef
pmodules.pas, proc_unit:
* if the initialization or finalization procedure is empty also remove their assembler symbols so they are exported
........
Ensure that readonly sections that need relocations are indeed declared as such.
Thanks to Jonas for this.
ncgvmt.pas, TVMTWriter:
* writeinterfaceids: use sec_rodata instead of sec_rodata_norel
........
git-svn-id: trunk@32982 -
The bug has been triggered only with the following conditions:
- tf_safecall_exceptions, tf_safecall_clearstack in target flags;
- fixed stack is used.
Since only the i386-android target meets these conditions atm, the bug has been unnoticed.
git-svn-id: trunk@32005 -
labels of LOC_JUMP in the node's location. This generates some extra jumps
for short circuit boolean and/or-expressions if optimizations are off, but
with optimisations enabled the generated code is the same (except for JVM
because the jump threading optimisation isn't enabled there yet).
git-svn-id: trunk@31431 -
type-safe way (for LLVM, and also internal consistency checking between
the VMT as generated in nobj.pas and ncgvmt.pas)
o also converted the VMT validity checking to the node level
git-svn-id: trunk@30950 -
the stack pointer during the prolog. This was done previously in
tcg.g_proc_entry(), but that routine is called after register allocation
and hence has no influence. Also cleaned up the deallocation of that
register by moving the previously ifdef'd code to thlcgppcgen
(mantis #27634)
git-svn-id: trunk@30164 -
platforms that normally must copy value parameters on the caller side,
because
o if we copy them on the caller side, then the behaviour will be different
compared to other platforms if the called routine is implemented in C
(since they are passed by reference, changes to the array contents will
be visible on other platforms, while they wouldn't be visible if the
copy is made on the caller side)
o if we don't copy them on the caller nor on the callee side, then behaviour
will be different compared to other platforms if the called routine is
implemented in Pascal and modifies the array (since then changes won't be
visible on the caller side, except on platforms that normally perform
the copy on the caller side)
git-svn-id: trunk@29873 -
be copied on the caller instead of callee side
o mark Darwin/Aarch64 as such a target (any AArch64 target will be like
that normally, as its ABI specifies this behaviour)
o don't mark by-reference value parameters on such targets as
vo_has_local_copy, since a) they don't have one (the copy is on the
caller side), and b) this ensures that all code handling such
parameters automatically knows that they are still by reference
after the init code has run
o when making the copies on the caller side, don't increase the
reference count for managed types except for variants, just like
is done when making the copies on the callee side. This is because
the reference count increasing code on the callee side only runs
for non-assembler functions, and we cannot know 100% certain on the
caller side whether the called function is assembler or not (e.g. in
case of externally declared functions)
o maybe over time we can reuse the Pascal code in
tcallparanode.copy_value_by_ref_para to replace the equivalent code
in hlcgobj and ncgutil also on the caller side for other targets
git-svn-id: trunk@29870 -
single register, by first storing everything consecutively to memory and
then loading it. Required for "homogeneous float aggregates" on AArch64
git-svn-id: trunk@29815 -
the code written in hlcg.gen_proc_symbol to avoid change from AB_LOCAL
to AB_GLOBAL, which generates erroneous code (at least for targets using GOT)
git-svn-id: trunk@29450 -
hardcoded registers for the most part)
+ added extra g_exception_discard_reason() that can be called when we only
want to get rid of the currently pushed exception reason, and don't have
to load it (so it can do nothing on platforms that don't use push/pop)
git-svn-id: branches/hlcgllvm@28481 -
be included at the start of the implementation of the system unit (before
the rest of except.inc)
* catch declarations in/loading from the system unit of the TExceptAddr type
* use this type instead of hardcoded size constants in the compiler
* in generic code that is active for all targets, puts its use in a virtual
method since it's only valid for targets using setjmp/longjmp-style
exception handling (and the record is not defined at all in the JVM RTL)
git-svn-id: branches/hlcgllvm@28376 -
Add support for .set and .weak on AVR.
Fix 64 bit negation on AVR.
Add cpu_capabilities to cpuinfo.pas and fixed some peephole optimizations.
Pass >4 byte parameters by reference.
git-svn-id: trunk@26943 -
This improves compiling speed a bit (two iterations over symtables replaced by one, code generator is created once per unit rather than once per class).
In perspective it makes possible to reduce amount of generated smartlink sections and global labels.
git-svn-id: trunk@24269 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
(avoids imaginary register number in "# Var I in register .." assembler comments.
* dbgdwarf.pas : Support register variables as register pairs.
Does not yet handle case of changing registers.
* symsym.pas : add currentregloc field to tabstractnormalvarsym class,
to be able to track changing registers used for a given variable.
* aasmtai.pas : Update currentregloc field of tai_varloc.create sym parameter.
* ncgutil.pas : Only generate a tai_varloc if the new registers are different for the variable.
git-svn-id: trunk@22508 -
