- xorq %reg,%reg (identical registers) is now changed to xorl %reg,%reg if doing so removes the REX prefix.
- movw %bx,%ax; andl $0xffff,%eax, for example, is now changed to movzwl %bx,%eax as long as a conditional operation doesn't follow 'and' (checks to see if the CPU flags are in use).
- movzbq and movzwq get optimised to movzbl and movzwl respectively if doing so removes the REX prefix.
- Removal of optimisation code that zero-extends from 32-bit to 64-bit, because there isn't actually a valid combination of opcodes for MOVZX that allows that (for registers,
just use MOV). This is not the case with MOVSX.
- movq is now optimised to movl even if the CPU flags are in use (this stops mov %reg,0 from being optimised to xor %reg,%reg if doing so breaks an algorithm that relies on them).
- Fixed typo in peephole message regarding movq to movl (it said movd instead).
- Made the peephole debug messages more consistent in formatting, some of which now have more detail.
* small fixes of the patch
git-svn-id: trunk@38070 -
- Moved the part that emits the CMOV command outside of the if-else block, because it's the same in both branches and was just duplicated code.
- Moved a comment about powers of 2 to be right before the correct if-else block.
- Added a couple of comments to explain what the algorithm is doing to obtain the remainder.
- Added missing "writeln('ok');" (since 'tmoddiv3.pp' has it) and program header to 'tmoddiv4.pp'.
- Changed program name from "testfile2" to "tmoddiv3" in 'tmoddiv3.pp'.
git-svn-id: trunk@37939 -
from cpubase unit to a method in the tcg class. The reason for doing that is
that this is now a standard part of the 16-bit and 8-bit code generators and
moving to the tcg class allows doing extra checks (not done yet, but for
example, in the future, we can keep track of whether there was an extra
register allocated with getintregister and halt with an internalerror in case
GetNextReg() is called for registers, which weren't allocated as a part of a
sequence, therefore catching a certain class of 8-bit and 16-bit code
generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
anything. It might be added to the tcg class, in case it's ever needed, but
for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.
git-svn-id: trunk@37180 -
(i386 and x86_64) code generator (same as the division by a positive power of
2, followed by a NEG instruction, to invert the sign of the result; previously
the code generator generated an IMUL instruction with a magic constant,
followed by shift; the new code sequence should be both shorter and faster)
git-svn-id: trunk@37003 -
with calls to cg.a_op_const_reg in the x86 div code generator, so that the
same code can be used in the future for i8086 as well (SHR and SAR by
constants other than 1 are 186+, so on 8086 they have to go through the CL
register, which is handled correctly in cg.a_op_const_reg)
git-svn-id: trunk@36815 -
o separate information for reading and writing, because e.g. in a
try-block, only the writes to local variables and parameters are
volatile (they have to be committed immediately in case the next
instruction causes an exception)
o for now, only references to absolute memory addresses are marked
as volatile
o the volatily information is (should be) properly maintained throughout
all code generators for all archictures with this patch
o no optimizers or other compiler infrastructure uses the volatility
information yet
o this functionality is not (yet) exposed at the language level, it
is only for internal code generator use right now
git-svn-id: trunk@34996 -
resulttype of the div node set by the type checking pass, this is
also how the generic code generator handles it, resolves#27173
git-svn-id: trunk@29382 -
