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bda163544a
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136 Commits

Author SHA1 Message Date
nickysn
bda163544a * tcg8086.g_flags2reg: restore the register back to the original size after the 
16-bit inc

git-svn-id: trunk@26337 -
 2013-12-31 13:15:30 +00:00
nickysn
fbd05c4e12 * Improved code generation in tcg8086.g_flags2reg for the case when target reg 
size is >=16-bit:
  o Generated code is now one instruction and one byte shorter.
  o No 8-bit subregisters are used, which reduces register pressure.

git-svn-id: trunk@26336 -
 2013-12-31 11:31:23 +00:00
nickysn
d57d982be7 * simpler handling of moves from a smaller to a larger cgsize in 
tcg8086.a_load_reg_ref, which additionally fixes the following issues:
  o The higher parts of the source register is no longer modified.
  o The source register's size is no longer modified with makeregsize.
  o Conversion from OS_S8 to a larger size is now supported.

git-svn-id: trunk@26335 -
 2013-12-31 00:33:37 +00:00
nickysn
5d0814016d * improvements and fixes in tcg8086.a_load_reg_reg and .a_load_ref_reg: 
o When expanding from a OS_8 to a 16-bit or 32-bit tcgsize, use the R_SUBH
    subregister to initialize the high 16 bits of the register to zero. This
    generates shorter and faster code, without increasing register
    interferences, because R_SUBH has the same register constraints on i8086 as
    R_SUBL, which is already used on the same imaginary register.
  o After performing operations on the 8-bit subparts of a register that was
    initially 16-bit, call makeregsize(OS_16) to notify the register allocator
    that the register is once again 16-bit.

git-svn-id: trunk@26328 -
 2013-12-30 21:20:10 +00:00
nickysn
6d48b32115 * fixes and improvements in tcg8086.a_load_reg_reg for the case when the src and 
dest are subregisters of the same superregister, but of different sizes:
   o Do not emit spurious moves from a register to the same register.
   o Correctly support the case when converting from 16-bit to 32-bit int.
     Previously it didn't work correctly, because in this particular case, due
     to the way the GetNextReg scheme works, we have reg1=reg2.

git-svn-id: trunk@26313 -
 2013-12-29 17:15:58 +00:00
nickysn
fdd36b4603 * on i8086 with regvars on, do not notify the register allocator of moves to BX. 
This fixes compilation of unit math (and the whole RTL) with regvars enabled.

git-svn-id: trunk@26282 -
 2013-12-25 12:19:21 +00:00
nickysn
dc432918da + enabled the use of the DIV/IDIV instruction for 16-bit div/mod on i8086 
* ti8086.moddivnode.pass_generate_code: use cg.a_op_const_reg, instead of
  emit_const_reg, in order to support generating plain 8086/8088 code
  (shr/shl/sar reg,const is 186+ if const is >= 2).

git-svn-id: trunk@26063 -
 2013-11-11 22:34:41 +00:00
nickysn
bd083c0b8e * ti8086moddivnode.pass_generate_code converted to 16-bit. Note that this code 
is still not active, due to the cpuneedsdiv32helper define, but will
  eventually be enabled for 16-bit divisions.

git-svn-id: trunk@26062 -
 2013-11-11 21:01:13 +00:00
nickysn
039979fdcc * handle 4-byte records in registers as well in location_force_mem on i8086 
git-svn-id: trunk@26002 -
 2013-11-09 21:57:29 +00:00
florian
f132a804d6 + handle 32 bit references on x86-64 so lea can be used for 32 bit arithmetics 
git-svn-id: trunk@25909 -
 2013-11-01 19:01:39 +00:00
nickysn
8bfe2a56dd * optimized SAR by 31 to use only one SAR instruction in tcg8086.a_op_const_reg 
git-svn-id: trunk@25883 -
 2013-10-30 16:53:59 +00:00
nickysn
645cd11b9d * fixed the assignment of global functions to nested procvars in i8086 far code 
models

git-svn-id: trunk@25831 -
 2013-10-19 20:42:39 +00:00
nickysn
bfd31e7516 * optimizations in tcg8086.g_copyvaluepara_openarray: 
- when elesize=2, avoid the SHR CX,1 instruction
  - use rep movsw even for odd elesizes, unless cs_opt_size is set

git-svn-id: trunk@25829 -
 2013-10-19 15:07:55 +00:00
nickysn
0f69362edd - rm LEA reg,imm from x86ins.dat, as that's not a valid x86 instruction, 
using it in inline asm causes an internal error and removing it didn't show
  any regressions after running the testsuite on i386-linux.

git-svn-id: trunk@25827 -
 2013-10-18 23:26:58 +00:00
nickysn
ff9ce0d20d * tcg8086.g_copyvaluepara_openarray improvements: 
- use a_op_const_reg for the multiplication, instead of emitting directly
    instructions, which are 186+
  - avoid using IMUL twice, when the element size is not power of two
  - rm the system_i386_win32 leftovers

git-svn-id: trunk@25826 -
 2013-10-18 22:35:51 +00:00
nickysn
7e7ab2fd4d * also handle nested proc ptrs in thlcgcpu.location_force_mem on i8086 
git-svn-id: trunk@25824 -
 2013-10-18 20:09:01 +00:00
nickysn
ef51c8c5a2 * fixed the interface wrapper code generation for virtual methods on i8086 in 
the medium memory model

git-svn-id: trunk@25817 -
 2013-10-18 12:11:50 +00:00
nickysn
116d3746ca * fixed the stack offset to the self parameter when generating an interface 
wrapper for a virtual method in tcg8086.g_intf_wrapper

git-svn-id: trunk@25816 -
 2013-10-18 10:56:04 +00:00
nickysn
83aa50de74 * emit a far jmp in the interface wrapper on i8086 in far code memory models 
git-svn-id: trunk@25812 -
 2013-10-17 21:55:45 +00:00
nickysn
4aa010eedc + support LEA with 16-bit operand size 
git-svn-id: trunk@25808 -
 2013-10-17 16:11:08 +00:00
nickysn
814e1297ed * tcg8086.g_adjust_self_value fixed for far code memory models 
git-svn-id: trunk@25798 -
 2013-10-15 23:34:18 +00:00
nickysn
f6e846c574 + added the NEC V20/V30 instructions 
git-svn-id: trunk@25750 -
 2013-10-11 21:27:56 +00:00
nickysn
0aff18ac61 + implemented tcg64f8086.a_op64_ref_reg 
git-svn-id: trunk@25707 -
 2013-10-07 00:17:03 +00:00
nickysn
3cdbf9a805 + implemented tcg64f8086.a_op64_const_ref 
git-svn-id: trunk@25706 -
 2013-10-06 23:56:25 +00:00
nickysn
3bdd3d9a4e + optimization in tcg64f8086.a_op64_const_reg for OP_ADD and OP_SUB when the 
lowest 48, 32 or 16 bits of the constant are zeros

git-svn-id: trunk@25705 -
 2013-10-06 23:43:38 +00:00
nickysn
88c7ca96c5 + optimization in tcg8086.a_op_const_reg and .a_op_const_ref for 32-bit OP_ADD 
and OP_SUB when the low 16 bits of the const are 0

git-svn-id: trunk@25704 -
 2013-10-06 23:23:06 +00:00
nickysn
8f44e729cc * tcg8086.a_op_const_ref and .a_op_const_reg: when splitting a 32-bit OP_AND, 
OP_OR or OP_XOR operation into two 16-bit parts, call a_op_const_reg/ref
  recursively for the 16-bit parts, so certain optimizations can be done if the
  low or high 16-bit of the const are $ffff.

git-svn-id: trunk@25703 -
 2013-10-06 23:02:07 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
sergei
5af873ee5b * x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files. 
git-svn-id: trunk@25627 -
 2013-10-03 08:08:04 +00:00
nickysn
4929bc5694 * regenerated the i8086 ins files 
git-svn-id: trunk@25603 -
 2013-09-28 21:10:23 +00:00
nickysn
bd0585274e * tsettings.enablecld converted to a targetswitch ts_cld 
git-svn-id: trunk@25592 -
 2013-09-28 13:41:58 +00:00
nickysn
52fcc0a407 + added a new x86-specific compiler option 'enablecld', which controls whether 
the compiler should emit a CLD before using the x86 string instructions.

git-svn-id: trunk@25590 -
 2013-09-28 11:54:02 +00:00
nickysn
1f783f539c * emit a cld instruction before the rep movsXX in tcg8086.g_copyvaluepara_openarray as well 
git-svn-id: trunk@25556 -
 2013-09-24 20:09:11 +00:00
nickysn
a04cbc09b0 * changed the default i8086 asmmode to Intel 
git-svn-id: trunk@25531 -
 2013-09-21 18:43:34 +00:00
nickysn
6aae88578c + getting the address of a label now returns a far pointer in i8086 far code memory models; this fixes the call to fpc_raiseexception in the raise node 
git-svn-id: trunk@25517 -
 2013-09-17 22:45:13 +00:00
nickysn
a5284881f5 + support 6-byte records in registers in thlcgcpu.location_force_mem on the i8086; this fixes the handling of methodpointers typecasted to record (TMethod) in medium and compact memory models 
git-svn-id: trunk@25500 -
 2013-09-16 16:24:00 +00:00
nickysn
b327eac688 - disable cs_opt_regvar from -O2 on i8086, since it's not working properly yet 
git-svn-id: trunk@25364 -
 2013-08-24 23:06:10 +00:00
florian
11ff8a4ec1 + support register parameters with multiple locations 
git-svn-id: trunk@25238 -
 2013-08-11 16:12:39 +00:00
nickysn
a5517cd3d4 * SI and DI removed from the i8086 saved_standard_registers list, because they are volatile in TP7's default calling convention 
git-svn-id: trunk@25231 -
 2013-08-09 12:21:30 +00:00
florian
57d4185d44 * allocate/deallocate cpu registers as late/early as possible, this gives the reg. allocator more flexibility 
git-svn-id: trunk@25229 -
 2013-08-08 20:55:45 +00:00
sergei
a21a20d559 + i8086-specific version of g_stackpointer_alloc. 
git-svn-id: trunk@25219 -
 2013-08-06 08:11:39 +00:00
nickysn
42e82c9de3 * when a i8086 reference uses only one register, choose it from the set [BX,BP,SI,DI] as it can be treated either as a base or an index, depending on what's convenient 
git-svn-id: trunk@25183 -
 2013-07-29 21:03:10 +00:00
nickysn
2e97de9522 + added an i8086 specific override of thlcgcpu.location_force_mem, which handles 6-byte (medium/compact memory model) method pointers 
git-svn-id: trunk@25151 -
 2013-07-20 19:40:27 +00:00
nickysn
f5a0702f9a + added i8086 specific implementation of Tcgtypeconvnode.second_nil_to_methodprocvar, which supports memory models with far code and/or far data 
git-svn-id: trunk@25150 -
 2013-07-20 16:58:41 +00:00
nickysn
4b93fa1323 * set all the i8086 calling conventions' volatile registers to be the same as the 'pascal' calling convention; this should make cdecl compatible with 16-bit C compilers 
git-svn-id: trunk@25128 -
 2013-07-18 21:01:41 +00:00
nickysn
2a64ba0ad3 * do a 32-bit comparison on far and huge pointers 
git-svn-id: trunk@25110 -
 2013-07-16 07:57:49 +00:00
nickysn
e291805880 * i8086 compilation fixed after r24896 
git-svn-id: trunk@24902 -
 2013-06-15 10:33:18 +00:00
nickysn
70dbd7f667 * far pointer aware conversion of method pointer to plain procvar 
git-svn-id: trunk@24863 -
 2013-06-10 09:56:45 +00:00
nickysn
b342588af1 + i8086 specific far proc aware implementation of ttypeconvnode.second_proc_to_procvar 
git-svn-id: trunk@24860 -
 2013-06-10 01:19:01 +00:00
nickysn
b81f0ab50d + implemented tcg8086.a_call_reg_far; very hacky, but still better than doing a near call, when it should be far 
git-svn-id: trunk@24856 -
 2013-06-09 22:16:40 +00:00