method by one with a lower visibility, because calling the overriding
method results in a java.lang.AbstractMethodError in that case
git-svn-id: trunk@21839 -
psub.pas: Use new fpc_compiler_has_fixup_jmps conditional.
mips/aasmcpu.pas: MIPS specific fixup_jmps function,
The insttruction distance calculation is not exact as
some pseudo-instruction can be expanded to a variable number of real instructions
real calculation would only be possible if we first
convert pseudo-instuctions to real instructions before calling fixup_jmps.
ncgutil.pas: Revert commit r21791
ncgcon.pas: Revert commit r21786
mips/cgcpu.pas: Partial revert of commit r21798, no need to always use A_J,
as fixup_jmps now handles out of range branches.
git-svn-id: trunk@21822 -
* test/tcg1.pp: rewrote without PIC, was having the same issue (GOT off by 1), additionally Intel syntax part won't compile anyway. This test is about push/pop encoding, not about PIC.
git-svn-id: trunk@21811 -
The old code forced dst and src to be the same, which is highly x86
specific and creates bad register utilization on other architectures
like arm.
The new version will use more imaginary registers, allowing the register
allocator to do a better job.
I've merged second_sar and second_rox into a single procedure
second_rox_sar because they were very similar.
git-svn-id: trunk@21809 -
RegInOp did not check for a register beeing part of a shifterop
(op.shifterop^.rs) which could result in trashed registers (But that did
not seem to happen yet anyway).
I've also implemented support for top_regset, but it is currently not
generated outside of proc_entry/proc_exit anyway.
git-svn-id: trunk@21808 -
This removes the duplications in a_op_reg_reg_reg_checkoverflow.
OP_ROL stays seperate because it needs some special treatment again.
The code for OP_ROL was changed, previously it generated:
mov tempreg, #32
sub src1, tempreg, src1
mov dst, src2, ror src1
This would trash src1, which MIGHT be a problem, but i'm not totally
sure. But the mov/sub was replaced with rsb, so the new code looks like
this.
rsb tempreg, src1, #32
mov dst, src2, ror tempreg
If src1 gets freed afterwards the regallocator should be able to change
that into:
rsb src1, src1, #32
mov dst, src2, ror src1
git-svn-id: trunk@21804 -
The previous code was full with duplicated code, this new version just
maps the OP_* to the correct SM_* and does some special handling for
OP_ROL which is done via OP_ROR.
git-svn-id: trunk@21801 -
