r28315 introduced an arm optimization which requires
tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.
git-svn-id: trunk@28360 -
* Moved handling of 64-bit values > high(int64) to qword_to_float64, so that normalizeRoundAndPackFloat64 procedure stays unmodified compared to C source.
* Using "jamming" right shift instead of regular one, so the least significant bit is not dropped but participates in rounding.
* Take a shortcut for values with <= 53 significant bits, which are convertible into float64 exactly and do not need rounding.
git-svn-id: trunk@28346 -
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.
git-svn-id: trunk@28344 -
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.
git-svn-id: trunk@28343 -
This is a very common construct in normal code and also heavily used in
softfpu code.
The ARM-cg will now just test for the MSB of reghi to be set, instead of
a full comparison against constant 0.
git-svn-id: trunk@28315 -
* int64_to_float64 and qword_to_float64: call 'function' overload of PackFloat64. Whenever arguments are constant it can be evaluated entirely at compile time (the procedure PackFloat64 does not have this property even if marked as inline because it is too complex, i.e. consists of more than single statement).
git-svn-id: trunk@28307 -
+ a_load_const_ref: use CLR and MOV3Q if possible.
* a_cmp_reg_reg_label: force size to 32 bits for ISA_A and ISA_A+ targets.
+ support for stack frames larger than 32767 bytes.
git-svn-id: trunk@28298 -
+ support spilling at offsets >32767, tested only to generate assemble-able code, support of large stack frames needs more changes elsewhere.
git-svn-id: trunk@28295 -
- for ftBlob parameters binding use temporary LOBs instead of long varraw to bypass 64KB limit of current implementation
- initial support for NCLOB data type (if client uses for NCHAR "variable width" charset (like UTF-8) then there is character length <> byte length which is currently not handled correctly)
git-svn-id: trunk@28286 -
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.
ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2
got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2
and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1
Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1
so r1 got loaded from a modified base-register.
This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.
git-svn-id: trunk@28284 -
