x86_64 is the most elaborated, has some degree of indirect function (GNU_IFUNC) and TLS support, so it is even able to link with static libc/pthreads code (tw14265) and produce an executable that can launch (but still fails due to invalid DWARF unwind info).
i386 produces working shared libraries if they are compiled with -Cg, without one your mileage may vary. tw14265 does not link yet due to missing COMDAT group support.
git-svn-id: trunk@22775 -
registers like the M68k): check whether the register type of the base/index register
of the instruction's reference is the same as the one we are doing register allocation
for. Otherwise the address registers can become corrupted.
git-svn-id: trunk@22748 -
* enable the 6 parameter syscall variant (still everything dummied out though)
* add termios constants
* don't change signal handlers for now
* disable assembly set routines as set handling was changed
git-svn-id: trunk@22743 -
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.
git-svn-id: trunk@22739 -
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).
git-svn-id: trunk@22738 -
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
out code a few lines further down)
git-svn-id: trunk@22736 -
It seems that GNU as needs the syntax "offset(register.size*scale)" if the base address
register is ommited instead of "offset(,register.size*scale)". Now the System unit
assembles and nearly the complete RTL can be built.
git-svn-id: trunk@22734 -
leave "and" and "or" as "and" and "or" as according to the assembly language reference the
assembler should automatically choose the correct instruction (though Coldfire still should
be tested for ORI/ANDI to CCR
git-svn-id: trunk@22733 -
* use andi/ori for constant values
* use a scratch register if target is an address register (there seems to exist an omnious
anda/ora instruction though, but GNU as doesn't seem to handle it... maybe I haven't set
the CPU type correctly, so I'll need to investigate this so we can hopefully remove the
need for a scratch register for certain CPU types ;) )
git-svn-id: trunk@22732 -
* remove comments regarding needed LOC_JUMP implementation
* don't call flags2reg if the location is LOC_JUMP as there isn't a register to set the flags to
(this allows fpc_mul_qword and fpc_mul_int64 to be assembled)
git-svn-id: trunk@22731 -
implement case "LOC_JUMP" (with a more or less blindly copy from
x86/nx86cnv.pas, tx86typeconvnode.second.int_to_bool; this now allows that the system unit can
be compiled, but not yet assembled
git-svn-id: trunk@22728 -
adjust syscalls just enough so that we don't have any duplicate symbols; the correctness will
be verified once we have linkable code
git-svn-id: trunk@22727 -
the asmr_d_*_reading messages need an argument which specifies in which style the assembler code
is read; this is most importantly used on i386; on m68k we currently don't have multiple styles,
so simply disable these messages
git-svn-id: trunk@22725 -
