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df199fbe23
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296 Commits

Author SHA1 Message Date
tg74
df199fbe23 bugfix 35700 xmmrm - zmmrm, mem32/64 
git-svn-id: branches/tg74/avx512merge@42956 -
 2019-09-08 19:13:42 +00:00
tg74
6a9e48c904 preparing for bugfix 35700 and cleanup 
git-svn-id: branches/tg74/avx512merge@42834 -
 2019-08-26 19:25:13 +00:00
tg74
9baf452681 Bugfix GATHER/SCATTER memref 
git-svn-id: branches/tg74/avx512merge@42723 -
 2019-08-18 04:39:36 +00:00
florian
46b4f91175 * compilation on i386-linux fixed 
git-svn-id: trunk@42675 -
 2019-08-13 09:45:13 +00:00
florian
413beee9ae -- Zusammenführen von r42652 bis r42673 in ».«: 
U    compiler/x86/aasmcpu.pas
-- Aufzeichnung der Informationen für Zusammenführung von r42652 bis r42673 in ».«:
 U   .

git-svn-id: trunk@42674 -
 2019-08-13 08:54:47 +00:00
tg74
ad791e8e34 bugfix error with avx-memory-parameter OT_MEM128,OT_MEM256,OT_MEM512 
git-svn-id: branches/tg74/avx512@42667 -
 2019-08-12 20:59:53 +00:00
florian
5947143d8f * intel asm reader: try to read avx512 extensions only if the instruction supports them 
* cleanup

git-svn-id: trunk@42656 -
 2019-08-12 10:46:19 +00:00
florian
4c9a0403f4 * compilation on i386 fixed 
git-svn-id: trunk@42655 -
 2019-08-11 19:35:34 +00:00
florian
f883dd6dbb Synchronized with trunk, part 2 (make all works, avx-512 support not yet tested, no regression testing yet) 
git-svn-id: branches/tg74/avx512@42643 -
 2019-08-10 19:38:35 +00:00
florian
746bfced25 Synchronized with trunk, part 1 (only make cycle tested, make all is broken, avx-512 support not yet tested 
git-svn-id: branches/tg74/avx512@42642 -
 2019-08-10 13:53:20 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
florian
4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 
+ avxopcodes tests also movbe and pclmulqdq

git-svn-id: trunk@40951 -
 2019-01-20 18:50:12 +00:00
florian
72416edcc4 + support for tlsm_general on i386-linux 
git-svn-id: trunk@40281 -
 2018-11-11 17:32:20 +00:00
yury
4357caaad8 * Removed unused local vars. 
git-svn-id: trunk@40183 -
 2018-11-02 18:44:29 +00:00
florian
cdce68451a - x86 align does not use a register anymore, code removed 
git-svn-id: trunk@40157 -
 2018-11-01 20:49:15 +00:00
tg74
60a75a2277 delete testcode 
git-svn-id: branches/tg74/avx512@39936 -
 2018-10-15 10:46:41 +00:00
tg74
1ef9cc01e6 avx512 disp8*N 
git-svn-id: branches/tg74/avx512@39909 -
 2018-10-09 21:19:52 +00:00
tg74
fba72b280b avx512 broadcast vcvt...,vfpclass... 
git-svn-id: branches/tg74/avx512@39778 -
 2018-09-19 15:28:15 +00:00
tg74
4265f4d6a5 avx512 broadcast for special opcodes vfpclass.., vcvt... 
git-svn-id: branches/tg74/avx512@39768 -
 2018-09-19 06:25:42 +00:00
tg74
3759eac608 bugfix avx512 add ZMMReg for gather/scatter in intelOS32 
git-svn-id: branches/tg74/avx512@39741 -
 2018-09-12 06:11:44 +00:00
tg74
8b9d7be8e5 bugfix OS32 
git-svn-id: branches/tg74/avx512@39719 -
 2018-09-10 06:18:48 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes 
git-svn-id: branches/tg74/avx512@39705 -
 2018-09-03 05:40:44 +00:00
tg74
5e1dc1a807 bugfix for test tasm9 32bit 
git-svn-id: branches/tg74/avx512@39695 -
 2018-09-01 08:26:18 +00:00
tg74
6f64177c6a bugfix avx512 OS32bit EVEX-coding 
git-svn-id: branches/tg74/avx512@39661 -
 2018-08-21 22:12:36 +00:00
tg74
29690162b8 bugfix OS32 
git-svn-id: branches/tg74/avx512@39650 -
 2018-08-19 18:41:45 +00:00
tg74
7c5cefad36 bugfix OS32 
git-svn-id: branches/tg74/avx512@39648 -
 2018-08-19 16:35:23 +00:00
tg74
7b8715184a bugfix OS32 
git-svn-id: branches/tg74/avx512@39647 -
 2018-08-19 16:31:09 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512 
git-svn-id: branches/tg74/avx512@39636 -
 2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register 
git-svn-id: branches/tg74/avx512@39457 -
 2018-07-16 17:06:57 +00:00
tg74
4dc5442fa5 support vector operand writemask,zeroflag 
git-svn-id: branches/tg74/avx512@39359 -
 2018-07-02 20:20:03 +00:00
tg74
31e4d4ef5e AVX512 support for MMRegister xmm16..31 and ymm16..31, zmm0..31, vpaddsb support AVX512 
git-svn-id: branches/tg74/avx512@39196 -
 2018-06-08 06:53:35 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd. 
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
 2018-03-03 23:32:54 +00:00
florian
f66a91499d * FPC uses meanwhile more mov instructions, so extended taicpu.is_same_reg_move to support them 
git-svn-id: trunk@38264 -
 2018-02-17 09:45:19 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton 
+ tests

git-svn-id: trunk@38206 -
 2018-02-11 17:50:37 +00:00
florian
e6a6938787 * make fpu/mmx/xmm/ymm registers numbers instead of flags to have enough space for zmm/bnd/k registers 
git-svn-id: trunk@38116 -
 2018-02-04 20:29:41 +00:00
nickysn
c464f7fa56 * fixed the SEG inline asm directive when used with 32-bit registers on the i8086 target 
git-svn-id: trunk@37613 -
 2017-11-22 15:04:30 +00:00
nickysn
8a0d8f025b * fixed another i8086 inline asm 32-bit constant bug (e.g. in 'or eax, 80000001h') 
git-svn-id: trunk@37521 -
 2017-10-25 19:38:37 +00:00
nickysn
325e66287c * fix for inline asm of instructions with 32-bit constant operands on i8086 
git-svn-id: trunk@37519 -
 2017-10-25 18:03:22 +00:00
nickysn
d7e4b50068 + also optimize x86_64 references by switching [rbp+reg64] to [reg64+rbp], 
[r13+reg64] to [reg64+r13] and [r13d+reg32] to [reg32+r13d]

git-svn-id: trunk@37516 -
 2017-10-24 16:18:43 +00:00
nickysn
5ae32a0ec5 + always do the x86_64 reference optimizations as if SS=DS, because the CPU 
basically ignores these segments in long mode

git-svn-id: trunk@37515 -
 2017-10-24 15:38:59 +00:00
nickysn
875339993f * strip segment overrides, for segments, which should be equal in the current 
model to the default segment of the reference in optimize_ref, when
  inlineasm=false

git-svn-id: trunk@37511 -
 2017-10-23 15:51:33 +00:00
nickysn
80226e3af4 + added an optimization pass, that optimizes x86 references 
git-svn-id: trunk@37494 -
 2017-10-20 15:55:55 +00:00
nickysn
67a0e9bdae + added x86 helper function get_default_segment_of_ref, which returns the 
default segment base for the ref, in case there's no segment override
* in the internal assembler, use get_default_segment_of_ref to strip redundant
  prefixes, instead of always assuming all refs are DS-based

git-svn-id: trunk@37486 -
 2017-10-18 14:24:58 +00:00
nickysn
6f2e64ff90 + added function get_ref_address_size 
git-svn-id: trunk@37470 -
 2017-10-16 14:13:03 +00:00
nickysn
b0653a6313 + added functions is_32_bit_ref and is_64_bit_ref, similar to is_16_bit_ref 
* taicpu.needaddrprefix now uses is_32_bit_ref on x86_64
* is_16/32/64_bit_ref made part of the aasmcpu unit interface, so they can be
  used elsewhere (e.g. in the inline assembler readers)

git-svn-id: trunk@37469 -
 2017-10-16 14:05:06 +00:00
nickysn
2b6e5d817e * changed the parameter of is_16_bit_ref to be a treference, instead of toper 
git-svn-id: trunk@37463 -
 2017-10-16 00:30:26 +00:00
nickysn
baf492c7a5 + another helper function: x86_parameterized_string_op_param_count 
* when generating x86 code for parameterized string instructions with the
  internal object writer, don't rely on the destination operand being [(r/e)di]
  when determining the segment prefix, because when using intel syntax, source
  and destination can be anything (only the operand size, the address size and
  the source segment is taken into account)

git-svn-id: trunk@37452 -
 2017-10-12 16:07:15 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions 
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
 2017-10-12 00:07:02 +00:00
nickysn
92a52a9f4d + implemented support for instructions with non-native address size on i8086 
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
  Known bug: 32-bit addresses with an offset have their offset truncated to its
  low 16-bits on i8086

git-svn-id: trunk@37409 -
 2017-10-06 15:27:14 +00:00
nickysn
8589b946fc * different versions (behind cpu specific ifdefs) of process_ea_ref renamed 
process_ea_ref_64_32, process_ea_ref_32 and process_ea_ref_16, indicating
  the address size they support; this is done, so that in the future, we can
  mix them all on the same x86 architecture and support multiple address sizes

git-svn-id: trunk@37407 -
 2017-10-05 22:15:26 +00:00