nickysn
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e43834c5d0
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* replace 'inc/dec orgreg' with 'inc/dec spilltemp' in trgcpu.do_spill_replace
git-svn-id: branches/z80@44552 -
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2020-04-03 22:19:40 +00:00 |
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florian
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a6cfaa996a
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* few cleanups towards building the z80-embedded system unit
git-svn-id: branches/z80@44550 -
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2020-04-03 20:37:27 +00:00 |
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florian
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d723b69325
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* regenerated
git-svn-id: branches/z80@44549 -
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2020-04-03 20:37:03 +00:00 |
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florian
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7ec42f5dc2
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* merge artefacts removed
git-svn-id: branches/z80@44548 -
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2020-04-03 20:31:51 +00:00 |
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florian
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89741ddeb5
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* lazarus version updated
git-svn-id: branches/z80@44547 -
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2020-04-03 20:25:47 +00:00 |
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florian
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0fc1ba26f8
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* compilation fixed
git-svn-id: branches/z80@44546 -
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2020-04-03 20:25:31 +00:00 |
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nickysn
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9d545342f8
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* replace 'add/adc/sub/sbc/and/or/xor/cp A,orgreg' with 'add/adc/sub/sbc/and/or/xor/cp A,spilltemp' in trgcpu.do_spill_replace
git-svn-id: branches/z80@44537 -
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2020-04-03 20:05:42 +00:00 |
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nickysn
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a58bab4318
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+ replace 'ld orgreg,const' with 'ld spilltemp,const' in trgcpu.do_spill_replace
git-svn-id: branches/z80@44536 -
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2020-04-03 19:47:47 +00:00 |
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nickysn
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fe3f4a7447
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* fixes in trgcpu.do_spill_replace
git-svn-id: branches/z80@44535 -
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2020-04-03 19:41:39 +00:00 |
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nickysn
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8ceee70912
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* range check for spilltemp.offset in [-128..127], not [0..63] in trgcpu.do_spill_replace for Z80
git-svn-id: branches/z80@44534 -
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2020-04-03 19:32:10 +00:00 |
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nickysn
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8291d24b7f
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* fix comment
git-svn-id: branches/z80@44533 -
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2020-04-03 18:53:52 +00:00 |
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nickysn
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bf8d560cc6
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* treat all Z80 registers as 8-bit
git-svn-id: branches/z80@44532 -
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2020-04-03 18:53:10 +00:00 |
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nickysn
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5ddd0dd9b8
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+ implemented a_load_const_ref for more efficient Z80 code generation for const assignment to local variables
git-svn-id: branches/z80@44528 -
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2020-04-03 02:23:05 +00:00 |
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nickysn
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4fe04ac53a
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* write references of the type (IX+const), (IY+const) as const(IX) or const(IY), since that appears to
be what sdcc-sdasz80 accepts
git-svn-id: branches/z80@44527 -
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2020-04-03 01:33:41 +00:00 |
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nickysn
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4099c0eed8
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+ initial implementation (not working yet) for spilling_create_store and spilling_create_load for Z80
git-svn-id: branches/z80@44526 -
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2020-04-03 01:03:49 +00:00 |
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nickysn
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e04d2acd6c
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+ emit references with negative offsets correctly in the sdcc-sdasz80 asm output
git-svn-id: branches/z80@44525 -
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2020-04-03 00:54:22 +00:00 |
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nickysn
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4de1d5a8bf
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+ Z80 stackframe generation
git-svn-id: branches/z80@44524 -
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2020-04-03 00:15:24 +00:00 |
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nickysn
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574fea7e63
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+ ait_tempalloc asm output for sdcc-sdasz80
git-svn-id: branches/z80@44523 -
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2020-04-02 23:29:52 +00:00 |
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nickysn
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4b281dd6c9
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* changed the ifndef avr to ifdef avr in GetNextReg
git-svn-id: branches/z80@44522 -
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2020-04-02 23:05:49 +00:00 |
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nickysn
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71cadc0a3e
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* moved the AVR-specific comment next to the AVR specific code
git-svn-id: branches/z80@44521 -
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2020-04-02 23:04:45 +00:00 |
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nickysn
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54811831b5
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- disable the check for R_SUBWHOLE in GetNextReg for Z80
git-svn-id: branches/z80@44520 -
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2020-04-02 23:02:55 +00:00 |
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nickysn
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f81c4a9454
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* synchronize with trunk
git-svn-id: branches/z80@44519 -
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2020-04-02 22:55:11 +00:00 |
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Jonas Maebe
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d5de84c6c5
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* use typenames in more cases in the generated LLVM IR (results in smaller
IR in textual form)
git-svn-id: trunk@44518 -
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2020-04-02 21:21:44 +00:00 |
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Jonas Maebe
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afd0ae44ee
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* use tprocvardef.getreusableprocaddr also for non-address-only copies of
proc(var)defs
git-svn-id: trunk@44517 -
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2020-04-02 21:21:40 +00:00 |
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Jonas Maebe
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4ba19f5418
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* add support for creating non-address-only procvars to
cprocvar.getreusableprocaddr()
git-svn-id: trunk@44516 -
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2020-04-02 21:21:36 +00:00 |
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florian
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b033ccbddb
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* cleanup
git-svn-id: trunk@44515 -
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2020-04-02 20:04:03 +00:00 |
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florian
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44d9498eff
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* cosmetics
git-svn-id: trunk@44514 -
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2020-04-02 20:04:02 +00:00 |
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nickysn
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65efc495af
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+ add edges to disallow the use of the 8-bit subregisters of IX, IY and SP
git-svn-id: branches/z80@44513 -
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2020-04-02 02:28:14 +00:00 |
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nickysn
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20cd3a6d1b
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- removed GetLoad and GetStore from tcgz80. These came from AVR and I don't think they would be useful
for Z80.
git-svn-id: branches/z80@44512 -
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2020-04-02 02:20:34 +00:00 |
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nickysn
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c02fc4a49f
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* fixed OP_NOT in tcgz80.a_op_reg_reg_internal
git-svn-id: branches/z80@44511 -
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2020-04-02 02:14:21 +00:00 |
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nickysn
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052313d649
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* fixed OP_AND,OP_OR,OP_XOR in tcgz80.a_op_reg_reg_internal
git-svn-id: branches/z80@44510 -
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2020-04-02 02:04:18 +00:00 |
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nickysn
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d7675c6c81
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+ support line info (-al) in the sdcc-sdasz80 asm output
git-svn-id: branches/z80@44509 -
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2020-04-02 01:19:17 +00:00 |
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nickysn
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cae1865f32
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* fixes for OP_ADD and OP_SUB in a_op_reg_reg_internal. The destination of add/adc/sub/sbc can only be
register NR_A.
git-svn-id: branches/z80@44508 -
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2020-04-02 01:10:52 +00:00 |
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nickysn
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d26b5199c8
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+ implemented a_load_ref_reg for fromsize=tosize for z80
git-svn-id: branches/z80@44507 -
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2020-04-02 01:01:58 +00:00 |
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nickysn
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3893baabd8
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+ output nothing for ait_stab, ait_force_line and ait_function_name in the sdcc-sdasz80 asm writer
git-svn-id: branches/z80@44506 -
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2020-04-02 00:50:49 +00:00 |
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nickysn
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73e11ee97d
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+ compile with -dEXTDEBUG
git-svn-id: branches/z80@44505 -
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2020-04-01 23:59:11 +00:00 |
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nickysn
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065a0d44d8
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* tcg64favr renamed tcg64fz80
git-svn-id: branches/z80@44504 -
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2020-04-01 23:32:02 +00:00 |
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nickysn
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50e5b07568
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* synchronize with trunk
git-svn-id: branches/z80@44503 -
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2020-04-01 22:43:55 +00:00 |
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nickysn
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fc80874e63
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+ implemented a_load_reg_reg for z80 for fromsize=tosize
git-svn-id: branches/z80@44502 -
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2020-04-01 22:43:10 +00:00 |
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nickysn
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662ca13f51
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* use register NR_A in a_load_reg_ref for z80
git-svn-id: branches/z80@44501 -
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2020-04-01 22:40:02 +00:00 |
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nickysn
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54097433da
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+ implemented cgsize2subreg for z80
git-svn-id: branches/z80@44500 -
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2020-04-01 22:29:33 +00:00 |
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nickysn
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c3ac9d06c8
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+ support ait_datablock in the sdcc-sdasz80 asm output
git-svn-id: branches/z80@44499 -
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2020-04-01 22:13:47 +00:00 |
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nickysn
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fbadb3519f
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+ implemented a_load_reg_ref for equal sized args for z80
git-svn-id: branches/z80@44498 -
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2020-04-01 22:08:46 +00:00 |
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nickysn
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fe5daf3d2f
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+ initial implementation of top_ref reference output for sdcc-sdasz80
git-svn-id: branches/z80@44497 -
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2020-04-01 22:08:22 +00:00 |
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marco
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07ee8948aa
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* use a PO flag to run idle event. This allows both cases (slow, long term input, and short, quick input) to run without derivation of the class for runcommand.
git-svn-id: trunk@44496 -
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2020-04-01 21:12:10 +00:00 |
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florian
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ba9e930556
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* Xtensa: set fpu type dependending on the controller
git-svn-id: trunk@44495 -
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2020-04-01 20:08:23 +00:00 |
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florian
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c2cf21d176
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+ Xtensa: boolean registers * Xtensa: register numbers of floating point registers corrected
git-svn-id: trunk@44494 -
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2020-04-01 20:08:22 +00:00 |
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florian
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1e0640c9e9
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* Xtensa: FreeRTOS uses windowed calling convention
git-svn-id: trunk@44493 -
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2020-04-01 20:08:21 +00:00 |
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florian
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b41c8342c8
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* Xtensa: reduce stack usage
git-svn-id: trunk@44492 -
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2020-04-01 20:08:20 +00:00 |
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nickysn
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b1ea62f5f6
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+ implemented ait_regalloc asm output for sdcc-sdasz80
git-svn-id: branches/z80@44491 -
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2020-04-01 19:05:22 +00:00 |
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