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ed984e0c76
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Author SHA1 Message Date
nickysn
ed984e0c76 - removed missing file from project 
+ compile with the EXTDEBUG define to catch more errors

git-svn-id: trunk@36025 -
 2017-04-30 20:48:35 +00:00
nickysn
b17d97050f + also simplify rol(x,0) and ror(x,0) to x 
git-svn-id: trunk@36024 -
 2017-04-30 20:45:51 +00:00
nickysn
8ac84ce43a + simplify sar(x,0) to x 
git-svn-id: trunk@36023 -
 2017-04-30 20:24:44 +00:00
nickysn
d8ec0eff8e + implemented inline code generation for 64-bit sar (the SarInt64 intrinsic) on 
less-than-64-bit CPUs that have a 64-bit OP_SHR/OP_SHL/OP_SAR implementation
  in their cg64 backend code generator. This is enabled only for i386 for now.

git-svn-id: trunk@36022 -
 2017-04-30 16:06:34 +00:00
nickysn
4e4e5d6d07 + allocate and free the flags register (when necessary), when generating code 
for OP_SHR,OP_SHL and OP_SAR in tcg64f8086.a_op64_const_reg

git-svn-id: trunk@36021 -
 2017-04-30 01:25:54 +00:00
Károly Balogh
a25912da0d fcl-passrc: fixed build broken since r36006 
git-svn-id: trunk@36020 -
 2017-04-29 22:56:12 +00:00
Károly Balogh
01ebb52ba8 morphos: added tf_needs_smybol_type and tf_needs_symbol_size flags. fixes generated executables to not be falsely recognized as PowerUP but native binaries 
git-svn-id: trunk@36019 -
 2017-04-29 22:31:41 +00:00
nickysn
b8c4dd9e18 + implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and 
use it in the shl/shr node for code generation.

git-svn-id: trunk@36018 -
 2017-04-29 21:57:48 +00:00
nickysn
a82c89d894 + implemented OP_SHR,OP_SHL and OP_SAR in a_op64_const_reg for i8086. The shlshr 
node now uses them for 64-bit shift by constant.

git-svn-id: trunk@36017 -
 2017-04-29 20:58:55 +00:00
Mattias Gaertner
20cd2d9ded pastojs: clean up 
git-svn-id: trunk@36007 -
 2017-04-29 10:51:34 +00:00
Mattias Gaertner
d7163d3854 fcl-passrc: parser: create usesclause 
git-svn-id: trunk@36006 -
 2017-04-29 10:50:00 +00:00
nickysn
d5d53e7017 * fixed operand order in the check for sse movsd in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@36003 -
 2017-04-28 14:56:54 +00:00
marco
2a82951f18 * fix compilation after last commit. make clean all in ide/ doesn't build all, and weditor 
had a local definition of rtrim

git-svn-id: trunk@35998 -
 2017-04-28 13:58:59 +00:00
nickysn
8926adbab5 * fixed names, returned by std_regname for ymm registers 
git-svn-id: trunk@35997 -
 2017-04-28 13:46:57 +00:00
nickysn
a9617b623f + print info about the registers, in which new values are written (as reported 
by RegLoadedWithNewValue), when DEBUG_INSTRUCTIONREGISTERDEPENDENCIES is
  defined

git-svn-id: trunk@35996 -
 2017-04-28 13:14:12 +00:00
nickysn
66c350d8d2 * fixed access violation bug in TX86AsmOptimizer.RegLoadedWithNewValue for the 
A_MOVSD string instruction

git-svn-id: trunk@35995 -
 2017-04-28 13:09:27 +00:00
marco
e837a8577c * use rtrim instead of a dec(s[0]) method after remark by jc99 
git-svn-id: trunk@35992 -
 2017-04-28 11:44:15 +00:00
nickysn
e6e55b3004 + added function TX86AsmOptimizer.Reg1ReadDependsOnReg2, which checks whether 
two registers are independent (taking into account AH vs AL)

git-svn-id: trunk@35991 -
 2017-04-28 09:24:48 +00:00
nickysn
33f9b36a54 + added and implemented function TX86AsmOptimizer.Reg1WriteOverwritesReg2Entirely, 
which takes into account how 16-bit and 8-bit subregisters work on the x86
  (the new function is not used for now, but is probably going to replace
  SuperRegistersEqual in a few specific places (in RegLoadedWithNewValue),
  so that our register tracking becomes more accurate for 8-bit and 16-bit
  subregisters)

git-svn-id: trunk@35990 -
 2017-04-27 22:30:47 +00:00
nickysn
aee000a773 * i8086's TCpuAsmOptimizer made a descendant of TX86AsmOptimizer 
git-svn-id: trunk@35985 -
 2017-04-27 18:22:14 +00:00
nickysn
a018235811 * fixed powerpc compiler compilation with -dEXTDEBUG 
git-svn-id: trunk@35982 -
 2017-04-27 17:25:33 +00:00
marco
a724265923 * more setlength 
git-svn-id: trunk@35979 -
 2017-04-27 16:57:44 +00:00
marco
ebdfaf6b0e * more s[0] elimination. 
git-svn-id: trunk@35973 -
 2017-04-27 16:20:37 +00:00
marco
75eea3c220 * s[0] ->setlength(s, first round, to ease experimentation with ansistrings 
git-svn-id: trunk@35970 -
 2017-04-27 16:03:51 +00:00
nickysn
ff1ee6836d + fix RegReadByInstruction for the x86 MOVSD instruction 
git-svn-id: trunk@35968 -
 2017-04-27 14:42:08 +00:00
nickysn
7ea0429d40 + added new compiler debug ifdef DEBUG_INSTRUCTIONREGISTERDEPENDENCIES, which 
adds instruction register usage info to the assembly output (only register
  reads for now, but register writes will also be added later). Useful for
  debugging InstructionLoadsFromReg and other similar functions.

git-svn-id: trunk@35967 -
 2017-04-27 13:40:58 +00:00
michael
fe2df71ef5 * Fix bug ID #31718 
git-svn-id: trunk@35966 -
 2017-04-27 12:34:17 +00:00
nickysn
b741e38f98 + precise handling for x86 conditions and their flag bits in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@35965 -
 2017-04-27 12:07:48 +00:00
Mattias Gaertner
09504f95f9 fcl-passrc: passrcutil, paswrite: using usesclause 
git-svn-id: trunk@35964 -
 2017-04-27 11:45:36 +00:00
Mattias Gaertner
0a88d5465f fcl-passrc: pastree: added TPasUsesUnit, elementtypenames for sections 
git-svn-id: trunk@35963 -
 2017-04-27 11:30:28 +00:00
nickysn
8512f8240e + enable constant propagation across 2-parameter inc()/dec() calls 
git-svn-id: trunk@35962 -
 2017-04-26 23:21:44 +00:00
nickysn
012153201a * moved the conversion of "x:=x op k" to inline nodes to a separate optimization 
pass, so that it can be done after other optimizations, such as constant
  propagation

git-svn-id: trunk@35961 -
 2017-04-26 22:44:01 +00:00
michael
3655388cae * Fix bug #31719 
git-svn-id: trunk@35960 -
 2017-04-26 21:18:10 +00:00
Jonas Maebe
aa82e00615 * fixed check to determine whether a record parameter can be subscripted 
directly in inline assembly: that's only possible if it's a register
    parameter where the address of the record was passed (rather than the
    record itself), or if a parameter has been explicitly typecasted in
    Intel-style assembly using ".size"

git-svn-id: trunk@35959 -
 2017-04-26 19:43:35 +00:00
nickysn
0f010430cc + better precision in determining the registers, read by mul/imul/div/idiv in 
i386's TCpuAsmOptimizer.RegReadByInstruction:
  * mul doesn't read edx (unless included in operand)
  * 8-bit mul and imul don't read ah (unless included in operand)
  * 8-bit div and idiv don't read edx (unless included in operand)

git-svn-id: trunk@35958 -
 2017-04-26 16:17:31 +00:00
nickysn
916c09af55 + also check the register type when checking for specific integer registers in 
i386's TCpuAsmOptimizer.RegReadByInstruction. Previously, the lack of this
  check could generate false reads on some other register types (e.g. mmx/xmm/
  flags, etc.), and this could worsen optimizations.

git-svn-id: trunk@35957 -
 2017-04-26 15:25:38 +00:00
nickysn
618b6292ee + support testing for individual bits from the x86 flags register in i386's 
TCpuAsmOptimizer.RegReadByInstruction()

git-svn-id: trunk@35956 -
 2017-04-26 14:38:36 +00:00
nickysn
c8487c4150 + added individual bits of the x86 flags register as subregisters 
git-svn-id: trunk@35955 -
 2017-04-26 13:52:52 +00:00
michael
3c53796044 * Fix memleak in case only a selection of tests is run 
git-svn-id: trunk@35954 -
 2017-04-26 13:24:42 +00:00
nickysn
5f66f5cebb + distinguish between x86 flags subregisters: flags, eflags and rflags 
git-svn-id: trunk@35953 -
 2017-04-25 16:10:43 +00:00
nickysn
65977f9f27 + implemented OP_ROL and OP_ROR in tcg8086.a_op_reg_reg and .a_op_reg_ref 
git-svn-id: trunk@35952 -
 2017-04-25 13:46:20 +00:00
michael
5d75dd6a32 * Support for escaped keywords using & ( bug ID #31708) 
git-svn-id: trunk@35951 -
 2017-04-25 13:35:02 +00:00
michael
f5b8292b6e * Fix bug #31709 
git-svn-id: trunk@35950 -
 2017-04-25 12:49:03 +00:00
michael
2b67d4c727 * Fix previous test 
git-svn-id: trunk@35949 -
 2017-04-25 12:25:54 +00:00
michael
60de96894a * Fix bug ID #31710: var,const,type sections can be empty in a class. 
git-svn-id: trunk@35948 -
 2017-04-25 12:25:13 +00:00
michael
874d6b0a09 * Fix bug ID #31710: var,const,type sections can be empty in a class. 
git-svn-id: trunk@35947 -
 2017-04-25 12:22:51 +00:00
marco
5d317a4e46 * manual CSE for fcomponents[i] in FindComponent, mantis #31628 
git-svn-id: trunk@35946 -
 2017-04-25 11:34:25 +00:00
nickysn
8c200fcfba + implemented OP_SHR,OP_SHL,OP_SAR,OP_ROL and OP_ROR in tcg8086.a_op_const_ref 
git-svn-id: trunk@35945 -
 2017-04-25 11:06:12 +00:00
pierre
c2ec612f1f Makefiel regenerated after commit 35943: Add testppudump rule in tests/tstunits directory 
git-svn-id: trunk@35944 -
 2017-04-24 21:16:51 +00:00
pierre
ca23830b56 Add testppudump rule in tests/tstunits directory 
git-svn-id: trunk@35943 -
 2017-04-24 21:16:15 +00:00