Commit Graph

15 Commits

Author SHA1 Message Date
Pierre Muller
acf5675a90 Change AVOID_OVERFLOW to avoid warning about inequality being always true 2023-10-26 07:47:10 +00:00
Pierre Muller
b521ac967f Fix possible overflow in riscv32 compiler 2023-10-26 01:02:20 +00:00
Jeppe
c83e6c34a9 riscv32: Fix 64bit comparisons
- Code taken from MIPS backend
- Removed some unused code generated for RV32 64bit integer ops
2022-10-16 17:37:53 +02:00
florian
e2a26ecece * fixes tcg64frv.a_op64_const_reg_reg based on the analysis of Bart B, resolves #39953 2022-10-13 23:16:19 +02:00
florian
a16f35dcb1 + support RV32E Extension 2022-07-17 22:14:13 +02:00
Jeppe
f5cf8956c5 riscv: Merge stack code, fix interrupted code
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
2022-07-02 15:07:42 +02:00
Jeppe
37b5147b19 riscv32: Fix potential FP proc_exit bug 2022-07-02 15:07:42 +02:00
florian
ca29df1aa9 * Risc-V: return with mret from interrupt handlers, resolves #39737 2022-05-27 23:33:20 +02:00
florian
03d353c1f5 - cosmetics: superfluous newlines removed
git-svn-id: trunk@48970 -
2021-03-14 16:41:34 +00:00
florian
d1881d0951 * RiscV: integer type conversions fixed
git-svn-id: trunk@48969 -
2021-03-14 16:40:14 +00:00
Jeppe Johansen
02c3f328a2 - RISC-V: Share optimizations between 32 and 64-bit.
git-svn-id: trunk@43934 -
2020-01-13 22:49:23 +00:00
Jonas Maebe
1e3f72403e * renamed getintparaloc to getcgtempparaloc
o it can be used for more than integer parameters

git-svn-id: trunk@43781 -
2019-12-24 22:12:25 +00:00
pierre
53a27fe7b3 Disable range check in m68k:tiscv32 and riscv64 cgcpu units
git-svn-id: trunk@40319 -
2018-11-15 16:58:40 +00:00
florian
44150f43ac * RISC-V 32 compilation fixed
+ lazarus project file for the compiler added

git-svn-id: branches/laksen/riscv_new@39511 -
2018-07-26 19:18:47 +00:00
Jeppe Johansen
ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00