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aasmcpu.pas
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* AVR: do not insert jmp if not supported
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2021-10-24 12:40:37 +02:00 |
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agavrgas.pas
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* LDD/STD need always an offset, resolves #33086
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2018-01-28 21:06:13 +00:00 |
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aoptcpu.pas
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* patch by Christo Crause: support for megaAVR 0 and tinyAVR 0/1, #36616, part 1/3
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2021-10-24 12:40:37 +02:00 |
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aoptcpub.pas
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aoptcpud.pas
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avrreg.dat
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ccpuinnr.inc
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- Adds intrinsics to save/restore SREG when disabling interrupts.
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2021-10-24 12:40:36 +02:00 |
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cgcpu.pas
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* patch by Christo Crause: support for megaAVR 0 and tinyAVR 0/1, #36616, part 1/3
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2021-10-24 12:40:37 +02:00 |
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cpubase.pas
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+ AVR: GetDefaultZeroReg and GetDefaultTmpReg
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2021-10-24 12:40:37 +02:00 |
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cpuinfo.pas
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* patch by Christo Crause: support for megaAVR 0 and tinyAVR 0/1, #36616, part 1/3
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2021-10-24 12:40:37 +02:00 |
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cpunode.pas
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+ implemented some AVR specific intrinsics
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2017-11-01 16:33:34 +00:00 |
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cpupara.pas
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+ AVR: initial support for the avrtiny architecture
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2021-10-24 12:40:37 +02:00 |
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cpupi.pas
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cputarg.pas
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hlcgcpu.pas
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itcpugas.pas
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navradd.pas
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+ AVR: GetDefaultZeroReg and GetDefaultTmpReg
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2021-10-24 12:40:37 +02:00 |
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navrcnv.pas
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navrinl.pas
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AVR: Add optimizations for sign testing, and a better Abs() implementation.
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2021-10-24 12:40:36 +02:00 |
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navrmat.pas
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* AVR: use CP ...,r1 instead of CPI ...,0 to enable all registers being used as first operand
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2021-10-24 12:40:37 +02:00 |
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navrmem.pas
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navrutil.pas
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raavr.pas
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* max_operands needs only to be 2 on avr
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2021-10-24 12:40:36 +02:00 |
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raavrgas.pas
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* keep track of the temp position separately from the offset in references,
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2018-04-22 17:03:16 +00:00 |
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ravrcon.inc
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ravrdwa.inc
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ravrnor.inc
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ravrnum.inc
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ravrrni.inc
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ravrsri.inc
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ravrsta.inc
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ravrstd.inc
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ravrsup.inc
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rgcpu.pas
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+ AVR: initial support for the avrtiny architecture
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2021-10-24 12:40:37 +02:00 |
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symcpu.pas
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tripletcpu.pas
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* merged macOS/AArch64 support + revisions these changes depended on
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2020-09-15 19:40:36 +00:00 |
