Pierre Muller 87e4931489 Fix fullcycle compilation error due to -Sew option ... Add 'else' branch to 'case' keyword construct for the setting of ABI in riscv32 assembler call. Do the same for riscv64 assembler call.		2023-06-14 08:19:06 +02:00
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aasmcpu.pas
agrvgas.pas	Fix fullcycle compilation error due to -Sew option	2023-06-14 08:19:06 +02:00
aoptcpurv.pas
cgrv.pas	* RiscV: generate mret only for FreeRTOS and Embedded	2022-07-20 22:16:19 +02:00
cpubase.pas	* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738	2022-06-03 22:54:18 +02:00
hlcgrv.pas
itcpugas.pas	+ forgotten pseudo-instructions added	2022-06-01 22:31:26 +02:00
nrvadd.pas	Fix internalerror generated with riscv32 compiler.	2022-10-25 18:42:14 +02:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas
nrvset.pas
rarv.pas
rarvgas.pas	* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738	2022-06-03 22:54:18 +02:00
rgcpu.pas
rvreg.dat	* unified Risc-V 32 and 64 register data file	2022-05-30 21:10:34 +02:00