sergei 4fc05e6ec1 - MIPS: removed taicpu.delayslot_annulled, it was a copy-paste from SPARC code. ... git-svn-id: trunk@33073 -		2016-02-09 01:32:42 +00:00
..
aasmcpu.pas	- MIPS: removed taicpu.delayslot_annulled, it was a copy-paste from SPARC code.	2016-02-09 01:32:42 +00:00
aoptcpu.pas	o refactored some peephole optimizer code:	2016-01-24 15:25:16 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* MIPS: Fixed code generation for PIC calls to local functions. Uncovered by r32803, before that the buggy branch was never taken because all functions were global.	2016-01-04 18:13:18 +00:00
cpubase.pas	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
cpuelf.pas	+ added class type property CObjSymbol to TExeOutput as well	2015-08-25 16:07:59 +00:00
cpugas.pas	- MIPS: removed taicpu.delayslot_annulled, it was a copy-paste from SPARC code.	2016-02-09 01:32:42 +00:00
cpuinfo.pas	Moved tcontrollerdatatype out into cpuinfo.	2015-09-07 20:36:54 +00:00
cpunode.pas
cpupara.pas	* support marking defs created via the getreusable*() class methods as	2015-11-04 20:46:18 +00:00
cpupi.pas
cputarg.pas
hlcgcpu.pas	* moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because	2014-08-19 20:22:54 +00:00
itcpugas.pas	* Removed unused vars for mipsel compiler.	2015-09-17 15:46:30 +00:00
mipsreg.dat	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
ncpuadd.pas	* Removed unused vars for mipsel compiler.	2015-09-17 15:46:30 +00:00
ncpucall.pas
ncpucnv.pas	* replaced current_procinfo.currtrue/falselabel with storing the true/false	2015-08-27 18:28:57 +00:00
ncpuinln.pas
ncpuld.pas
ncpumat.pas	* synchronised with r28168 of trunk	2014-07-05 21:30:28 +00:00
ncpuset.pas	* Removed unused vars for mipsel compiler.	2015-09-17 15:46:30 +00:00
opcode.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
racpugas.pas	* MIPS asm reader: parse dollar sign followed by identifier/number as a single token (register), not as two separate tokens.	2016-01-21 14:57:24 +00:00
rgcpu.pas	* synchronized with privatetrunk till r30095	2015-03-05 20:32:15 +00:00
rmipscon.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rmipsdwf.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgas.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsnum.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsrni.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssta.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsstd.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssup.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
strinst.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
symcpu.pas	o fixes handling of iso i/o parameters/program parameters:	2015-05-01 20:58:31 +00:00