sergei 720b9bf560 * SPARC: reworked 64-bit comparisons so their result is always in flags. Comparisons are emitted as subtractions, sides are optionally swapped to avoid using Z flag (since it is not set correctly in multi-word subtraction). This generates significantly shorter code: when both sides are in registers it is just 3 instructions for equal/unequal and 2 instructions otherwise. ... git-svn-id: trunk@26433 -		2014-01-12 15:11:47 +00:00
..
aasmcpu.pas
aoptcpu.pas
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	+ SPARC: support 8 and 16-bit arithmetic shifts.	2013-12-30 23:37:21 +00:00
cpubase.pas	* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.	2013-12-27 06:45:49 +00:00
cpuelf.pas	+ Added codes of dynamic relocations to TElfTarget; since most targets use similar dynamic relocation model differing only in code values, this will allow to do majority of handling in the base class.	2012-12-16 09:36:34 +00:00
cpugas.pas	* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.	2013-12-27 19:53:38 +00:00
cpuinfo.pas	* removed spaces from sparc cpu name strings so they can be much easier used	2012-10-31 20:57:14 +00:00
cpunode.pas
cpupara.pas	* SPARC: properly justify parameters on stack with size less than 4, fixes failure on tests/cg/tcalext5.pp	2013-12-28 09:23:10 +00:00
cpupi.pas	* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.	2013-12-27 19:53:38 +00:00
cputarg.pas	Add possibility to test sparc elf generator with -dTEST_AGSPARC_ELF	2012-08-23 12:59:45 +00:00
hlcgcpu.pas
itcpugas.pas
ncpuadd.pas	* SPARC: reworked 64-bit comparisons so their result is always in flags. Comparisons are emitted as subtractions, sides are optionally swapped to avoid using Z flag (since it is not set correctly in multi-word subtraction). This generates significantly shorter code: when both sides are in registers it is just 3 instructions for equal/unequal and 2 instructions otherwise.	2014-01-12 15:11:47 +00:00
ncpucall.pas	compiler: change ret_in_param to accept tabstractprocdef instead of tproccalloption to allow check more options (required for record constructor implementation)	2013-01-16 01:14:23 +00:00
ncpucnv.pas	* SPARC: convert from int64/qword to float using genmath helpers. Removes dependency on softfloat code.	2013-12-22 14:02:34 +00:00
ncpuinln.pas
ncpumat.pas	* SPARC, tmoddivnode improvements/fixes:	2014-01-03 08:09:32 +00:00
ncpuset.pas	* Proper fix for SPARC cycling with -dCHECK_PIC, pi_needs_got additionally must be set in following cases:	2012-12-18 17:56:56 +00:00
opcode.inc	+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.	2013-12-21 16:27:24 +00:00
racpu.pas
racpugas.pas	* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.	2013-12-27 06:45:49 +00:00
rgcpu.pas	+ SPARC: implemented register spill replacement.	2014-01-03 08:14:43 +00:00
rspcon.inc
rspdwrf.inc
rspnor.inc
rspnum.inc
rsprni.inc
rspsri.inc
rspstab.inc
rspstd.inc
rspsup.inc
spreg.dat
strinst.inc	+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.	2013-12-21 16:27:24 +00:00