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aoptcpu.pas
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aoptcpub.pas
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aoptcpuc.pas
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aoptcpud.pas
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cgcpu.pas
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* Risc-V: make use of sext.h instruction if available
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2024-08-15 21:53:04 +02:00 |
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cpuinfo.pas
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+ RiscV: support ZMMUL extension
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2025-01-26 14:43:57 +01:00 |
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cpunode.pas
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+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0
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2025-01-11 21:03:54 +01:00 |
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cpupara.pas
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* RiscV: push_addr_param unified
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2024-12-26 16:49:43 +01:00 |
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cpupi.pas
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cputarg.pas
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+ first work for esp32-c3 support
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2023-01-28 21:28:19 +01:00 |
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hlcgcpu.pas
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nrv32add.pas
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riscv32: Fix 64bit comparisons
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2022-10-16 17:37:53 +02:00 |
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nrv32cal.pas
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nrv32cnv.pas
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nrv32mat.pas
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Fix compilation of riscv32 compiler
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2025-01-10 12:10:02 +00:00 |
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nrv32util.pas
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* fixes RiscV32 building
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2024-12-25 22:48:40 +01:00 |
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rrv32con.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32dwa.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32nor.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32num.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32rni.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32sri.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32sta.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32std.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv32sup.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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symcpu.pas
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tripletcpu.pas
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