..
aasmcpu.pas
* MIPS: emit PIC-friendly instruction sequences instead of "J" when fixing up branches outside of 128K range. Resolves #25399 .
2013-12-11 10:56:07 +00:00
aoptcpu.pas
+ MIPS: implemented peephole optimization which changes appropriate patterns into conditional moves, which are available on MIPS4 and higher.
2014-06-20 05:57:39 +00:00
aoptcpub.pas
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
2012-06-07 23:20:06 +00:00
aoptcpud.pas
cgcpu.pas
+ Support (as target-independent as possible) optimization of division by constants:
2014-06-08 22:50:24 +00:00
cpubase.pas
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
cpuelf.pas
+ MIPS internal linker: support TLS IE/LE and GPREL32 relocations, is now able to link tw14265.
2013-07-29 09:30:40 +00:00
cpugas.pas
* MIPS: dropped gas_std_regname, its functionality merged into std_regname. This fixes register names in non-instructions (reg. allocation information, variable locations, etc.) and makes assembler listings more readable.
2014-06-16 22:52:56 +00:00
cpuinfo.pas
* MIPS: re-enable peephole optimizations which got disabled by r27106 and were not restored in r27147. Unfortunately such things are hard to detect reliably in automated way.
2014-06-04 22:34:46 +00:00
cpunode.pas
+ support overriding tdef/tsym methods with target-specific functionality:
2014-03-29 22:31:55 +00:00
cpupara.pas
* MIPS: floating point parameters on stack should be loaded to/from FPU registers directly, without using temp.
2013-07-17 11:00:46 +00:00
cpupi.pas
* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.
2014-04-02 14:17:23 +00:00
cputarg.pas
* partially merged the mips-embedded branch of Michael Ring:
2014-03-19 21:25:38 +00:00
hlcgcpu.pas
* partially merged the mips-embedded branch of Michael Ring:
2014-03-19 21:25:38 +00:00
itcpugas.pas
* fix fpu register type
2012-02-05 09:14:55 +00:00
mipsreg.dat
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
2014-06-22 22:01:44 +00:00
ncpuadd.pas
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
2014-03-10 09:01:05 +00:00
ncpucall.pas
* MIPS: clean up
2014-03-04 08:42:45 +00:00
ncpucnv.pas
* MIPS: when converting int to real, use a floating point constant directly, instead of emulating it with integers. tai_real_64bit already handles all endian issues.
2013-10-26 18:12:25 +00:00
ncpuinln.pas
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
2014-03-10 09:01:05 +00:00
ncpuld.pas
- Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels.
2013-06-02 10:49:17 +00:00
ncpumat.pas
+ Support (as target-independent as possible) optimization of division by constants:
2014-06-08 22:50:24 +00:00
ncpuset.pas
* MIPS and SPARC: determine whether case expression is in range using a single unsigned comparison (like it is done on other targets).
2014-03-10 23:02:05 +00:00
opcode.inc
+ MIPS: added movn and movz instructions.
2014-06-19 22:44:17 +00:00
racpugas.pas
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
2014-06-22 22:01:44 +00:00
rgcpu.pas
- MIPS: completely removed trgcpu.add_constraints method.
2014-06-19 03:59:24 +00:00
rmipscon.inc
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
2014-06-22 22:01:44 +00:00
rmipsdwf.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsgas.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsgri.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsnum.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsrni.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipssri.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipssta.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsstd.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipssup.inc
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
2014-06-22 22:01:44 +00:00
strinst.inc
+ MIPS: added movn and movz instructions.
2014-06-19 22:44:17 +00:00
symcpu.pas
Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".
2014-04-11 14:30:59 +00:00
e367ccc0ee