florian 49aa141703 * major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests		2024-12-22 22:37:16 +01:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	* Risc-V: make use of sext.h instruction if available	2024-08-15 21:53:04 +02:00
cpuinfo.pas	+ more RiscV extensions	2024-11-17 15:05:35 +01:00
cpunode.pas	Add insert_init_final_table method	2024-05-25 17:26:15 +00:00
cpupara.pas	* major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests	2024-12-22 22:37:16 +01:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nrv32add.pas
nrv32cal.pas
nrv32cnv.pas
nrv32mat.pas	+ Risc-V 32: optimize QWord(1) shl ...	2024-07-28 21:17:25 +02:00
nrv32util.pas	Initial support for esp32-c6-s2-s3. Support for idf versions 5.0.6 and 5.2.1	2024-07-18 20:16:04 +00:00
rrv32con.inc
rrv32dwa.inc
rrv32nor.inc
rrv32num.inc
rrv32rni.inc
rrv32sri.inc
rrv32sta.inc
rrv32std.inc
rrv32sup.inc
symcpu.pas
tripletcpu.pas