Jeppe Johansen b98eb3daa9 Changed order in stack unravelling RTL code, to match the most common cases. ... Fixed unsigned conditions for branch conditions. Added some additional const loading cases. Changed the temporary register used during calls because it could otherwise clash with the argument passing registers. git-svn-id: branches/laksen/riscv_new@39492 -		2018-07-23 01:11:31 +00:00
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aoptcpu.pas	Added implementation of InstructionLoadsFromReg.	2018-07-22 18:38:07 +00:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	Changed order in stack unravelling RTL code, to match the most common cases.	2018-07-23 01:11:31 +00:00
cpubase.pas	Add RV64GC cpu type.	2018-07-21 22:34:42 +00:00
cpuinfo.pas	Add RV64GC cpu type.	2018-07-21 22:34:42 +00:00
cpunode.pas
cpupara.pas	Pass aggregates larger than 2*XLEN as a reference.	2018-07-22 14:15:29 +00:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
itcpugas.pas
nrv64add.pas
nrv64cal.pas
nrv64cnv.pas	* fix int to real for non-register locations	2018-07-22 20:48:15 +00:00
nrv64ld.pas
nrv64mat.pas
rarv64gas.pas
rarv.pas
rrv32con.inc
rrv32dwa.inc
rrv32nor.inc
rrv32num.inc
rrv32rni.inc
rrv32sri.inc
rrv32sta.inc
rrv32std.inc
rrv32sup.inc
rv32reg.dat
symcpu.pas