florian 72daf3f556 * RiscV64: optimize 32 bit shift instructions as well		2025-01-04 14:59:00 +01:00
..
aasmcpu.pas	* make use of LA pseudo-instruction	2024-12-25 18:35:46 +01:00
agrvgas.pas	* make use of LA pseudo-instruction	2024-12-25 18:35:46 +01:00
aoptcpurv.pas	* RiscV64: optimize 32 bit shift instructions as well	2025-01-04 14:59:00 +01:00
cgrv.pas	* make use of LA pseudo-instruction	2024-12-25 18:35:46 +01:00
cpubase.pas	* typo corrected	2024-12-02 22:45:34 +01:00
hlcgrv.pas
itcpugas.pas	+ Risc-V: instructions of B extension	2024-08-12 21:51:22 +02:00
nrvadd.pas	* RiscV: more reliable use_fma	2024-11-18 22:32:55 +01:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas	* fix trvinlinenode.second_fma	2025-01-01 18:00:15 +01:00
nrvset.pas	+ RiscV64: apply OptPass1OP also to addiw	2024-11-13 22:56:13 +01:00
nrvutil.pas	* write basic attributes for riscvXX-linux	2024-12-30 15:56:24 +01:00
pararv.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
rarv.pas	* unified RiscV32 and RiscV64 GAS readers	2021-03-07 08:53:03 +00:00
rarvgas.pas	* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738	2022-06-03 22:54:18 +02:00
rgcpu.pas
rvreg.dat	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00