Jonas Maebe f402b0d7df * changed getpointerdef() into a tpointerdef.getreusable() class method ... o allows removing the ugly x86 hacks git-svn-id: trunk@31144 -		2015-06-22 08:17:49 +00:00
..
aasmcpu.pas	* MIPS: fixed O_MOVE_SOURCE and O_MOVE_DEST constants (they were swapped, amazing that it ever worked with such a mistake).	2014-09-03 19:57:46 +00:00
aoptcpu.pas	* MIPS peephole: check that operand is present before accessing its fields, also check that it's not a branch target. Mantis #27608.	2015-03-06 00:04:06 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	+ added tasmlist parameter to getintparaloc() (needed for llvm)	2015-04-04 14:29:16 +00:00
cpubase.pas	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
cpuelf.pas	Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen).	2014-12-14 16:28:35 +00:00
cpugas.pas	* Fixed condition to output div/divu having R0 as first operand as non-macros.	2014-12-29 23:19:01 +00:00
cpuinfo.pas	+ change always floating point divisions into multiplications if they are a power of two,	2014-11-16 20:47:38 +00:00
cpunode.pas
cpupara.pas	* changed getpointerdef() into a tpointerdef.getreusable() class method	2015-06-22 08:17:49 +00:00
cpupi.pas
cputarg.pas
hlcgcpu.pas	* moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because	2014-08-19 20:22:54 +00:00
itcpugas.pas
mipsreg.dat	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
ncpuadd.pas	+ MIPS: implement inline full 64-bit multiplication, for cases when overflow checking is off and CPU is set to mips32r2.	2014-12-28 22:03:15 +00:00
ncpucall.pas
ncpucnv.pas	* correctly handle LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF in second_int_to_bool, resolves issue #28007	2015-05-02 13:52:50 +00:00
ncpuinln.pas
ncpuld.pas
ncpumat.pas	* synchronised with r28168 of trunk	2014-07-05 21:30:28 +00:00
ncpuset.pas
opcode.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
racpugas.pas	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rgcpu.pas	* synchronized with privatetrunk till r30095	2015-03-05 20:32:15 +00:00
rmipscon.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rmipsdwf.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgas.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsnum.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsrni.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssta.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsstd.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssup.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
strinst.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
symcpu.pas	o fixes handling of iso i/o parameters/program parameters:	2015-05-01 20:58:31 +00:00