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aoptcpu.pas
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* do no generated debug comment in assembler output of RiscV if not requested
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2024-05-25 20:16:42 +02:00 |
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aoptcpub.pas
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aoptcpuc.pas
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aoptcpud.pas
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cgcpu.pas
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* RiscV64: make use of zext.w instruction if available
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2025-02-19 22:44:03 +01:00 |
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cpuinfo.pas
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+ RV64GCB CPU type
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2025-02-20 22:41:35 +01:00 |
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cpunode.pas
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+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0
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2025-01-11 21:03:54 +01:00 |
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cpupara.pas
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* RiscV: push_addr_param unified
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2024-12-26 16:49:43 +01:00 |
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cpupi.pas
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cputarg.pas
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hlcgcpu.pas
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nrv64add.pas
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+ RiscV: support ZMMUL extension
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2025-01-26 14:43:57 +01:00 |
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nrv64cal.pas
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nrv64cnv.pas
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nrv64ld.pas
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nrv64mat.pas
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+ RiscV: make use of the fneg.* instruction
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2025-01-09 22:25:26 +01:00 |
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rrv64con.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64dwa.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64nor.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64num.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64rni.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64sri.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64sta.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64std.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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rrv64sup.inc
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+ RiscV: vector registers
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2024-12-25 10:34:46 +01:00 |
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symcpu.pas
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tripletcpu.pas
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* correct tripletcpustr, resolves #40301
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2023-05-31 20:26:50 +02:00 |
