sergei 482e61dafa * MIPS, TCpuAsmOptimizer.GetNextInstructionUsingReg: test that returned item is actually an instruction, because GetNextInstruction can sometimes stop on labels. ... + Try to eliminate register move after instructions that load from memory. git-svn-id: trunk@28380 -		2014-08-10 21:31:13 +00:00
..
aasmcpu.pas
aoptcpu.pas	* MIPS, TCpuAsmOptimizer.GetNextInstructionUsingReg: test that returned item is actually an instruction, because GetNextInstruction can sometimes stop on labels.	2014-08-10 21:31:13 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* Inserted explicit typecasts in order to prevent range check errors at some places where signed and unsigned types are assigned to each other (mostly MIPS-specific, but one was necessary in generic code).	2014-08-10 21:26:14 +00:00
cpubase.pas	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
cpuelf.pas
cpugas.pas	* MIPS: dropped gas_std_regname, its functionality merged into std_regname. This fixes register names in non-instructions (reg. allocation information, variable locations, etc.) and makes assembler listings more readable.	2014-06-16 22:52:56 +00:00
cpuinfo.pas	* MIPS: re-enable peephole optimizations which got disabled by r27106 and were not restored in r27147. Unfortunately such things are hard to detect reliably in automated way.	2014-06-04 22:34:46 +00:00
cpunode.pas	+ support overriding tdef/tsym methods with target-specific functionality:	2014-03-29 22:31:55 +00:00
cpupara.pas
cpupi.pas	* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.	2014-04-02 14:17:23 +00:00
cputarg.pas
hlcgcpu.pas
itcpugas.pas
mipsreg.dat	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
ncpuadd.pas
ncpucall.pas
ncpucnv.pas
ncpuinln.pas
ncpuld.pas
ncpumat.pas	+ Support (as target-independent as possible) optimization of division by constants:	2014-06-08 22:50:24 +00:00
ncpuset.pas
opcode.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
racpugas.pas	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rgcpu.pas	- MIPS: completely removed trgcpu.add_constraints method.	2014-06-19 03:59:24 +00:00
rmipscon.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rmipsdwf.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgas.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsnum.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsrni.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssta.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsstd.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssup.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
strinst.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
symcpu.pas	Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".	2014-04-11 14:30:59 +00:00