Interferon
8382c6f586
Added generic WCH32Vx RISC-V processor types using memory size suffixes
...
Modified low-level startup code for RISCV32 embedded microcontrollers to
allow user code override of reset handlers for non-power-up reset events
as well as enabling user code override handlers for all 255 possible
interrupt vectors.
Separated out the low-level startup memory init into a callable procedure
to allow users that have caught reset events to init memory again if needed.
Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
2023-08-26 22:12:00 +02:00
Pierre Muller
87e4931489
Fix fullcycle compilation error due to -Sew option
...
Add 'else' branch to 'case' keyword construct
for the setting of ABI in riscv32 assembler call.
Do the same for riscv64 assembler call.
2023-06-14 08:19:06 +02:00
Pierre Muller
0d256f517f
Set defualt riscv32 linux abi to abi_riscv_ipl32
2023-06-13 19:39:55 +00:00
florian
0e05e908d5
riscv32-freertos:
...
* unit name fixed
* linker script fixed
* assembler supports dwarf
2023-02-09 21:29:06 +01:00
florian
bedd4edc72
+ first work for esp32-c3 support
2023-01-28 21:28:19 +01:00
florian
a16f35dcb1
+ support RV32E Extension
2022-07-17 22:14:13 +02:00
florian
e047e7db91
+ RiscV: initial support of pic generation
...
git-svn-id: trunk@48947 -
2021-03-13 16:18:00 +00:00
florian
6f3fccddd1
* RiscV32: properly read references with record offsets and base register
...
+ RiscV32: sanity check in assembler writer
git-svn-id: trunk@48892 -
2021-03-06 22:19:00 +00:00
florian
5cd4e5a016
* pass lp64d to GNU AS for abi_riscv_hf to get the right ABI set
...
git-svn-id: trunk@47585 -
2020-11-25 20:20:08 +00:00
nickysn
3d81dd0b00
* ReplaceForbiddenAsmSymbolChars renamed ApplyAsmSymbolRestrictions, because now it also applies the
...
label length limit
git-svn-id: branches/z80@45085 -
2020-04-26 10:42:07 +00:00
nickysn
a8fe46c0f5
+ introduced labelmaxlen in tasminfo and added code in ReplaceForbiddenAsmSymbolChars that limits the
...
output label to that length
git-svn-id: branches/z80@45066 -
2020-04-25 12:59:25 +00:00
Jeppe Johansen
2678522db5
- RISC-V: Add controller types for common RV32 MCUs.
...
- Adds initial controller units for these MCUs.
Code contributed by Michael Ring
git-svn-id: trunk@43935 -
2020-01-13 22:54:26 +00:00
svenbarth
114c27fb4e
* increase support for multilib binutils for RISC V by passing the ABI to the assembler
...
git-svn-id: trunk@43788 -
2019-12-25 15:23:21 +00:00
Jeppe Johansen
a1a17447ff
- Fix bug in 64bit softfloat double negation.
...
- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.
git-svn-id: trunk@42335 -
2019-07-07 11:32:27 +00:00
Jonas Maebe
281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
...
be introduced by the next commit
git-svn-id: trunk@42046 -
2019-05-12 14:29:03 +00:00
Jeppe Johansen
29ea4ed07d
Add rounding mode operands.
...
Add support for trunc and round methods.
git-svn-id: branches/laksen/riscv_new@39698 -
2018-09-01 19:48:44 +00:00
Jeppe Johansen
f781c8942e
Write real atomic operations, and add memory barrier operations.
...
Add support for fence, and acquire/release syntax to assembler reader.
Fix broken register aliases.
git-svn-id: branches/laksen/riscv_new@39524 -
2018-07-29 16:43:09 +00:00
Jeppe Johansen
6352328f3a
Update packages with information about RiscV.
...
Fix g_external_wrapper, since it uses a register.
Fixed calling of gas.
Ported cprt0.
git-svn-id: branches/laksen/riscv_new@39475 -
2018-07-20 10:40:28 +00:00
Jeppe Johansen
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
...
git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00
