Commit Graph

438 Commits

Author SHA1 Message Date
Jonas Maebe
1c3fc6e2df * don't convert the fpu parameters size from tcgsize -> int -> float_tcgsize
if not required, to avoid translating OS_C64 into OS_F64 (fix for x86
    test failures after r45205)

git-svn-id: trunk@45221 -
(cherry picked from commit 3f6ad30b69)
2022-02-13 12:02:28 +01:00
Jonas Maebe
8a31764a7b * support floating point parameters split over multiple locations, including
integer registers, for homogeneous records/arrays on ppc64le (related to
    mantis #36934)

git-svn-id: trunk@45205 -
(cherry picked from commit 722ad1ff7b)
2022-02-13 12:01:36 +01:00
florian
3ef2ab1019 * cleaning up tcgsize: it makes no sense to declare every combination and type
the different vector types must be either handled in the high level cg or
    by using the shuffle parameter

git-svn-id: trunk@43860 -
(cherry picked from commit b7c6e01b03)
2022-02-13 12:00:45 +01:00
florian
feb9274963 * fix tcgobj.a_op_reg_ref and tcgobj.a_op_ref_reg after recent avr related merges 2021-10-24 12:40:38 +02:00
nickysn
c9d2028ebd * handle LOC_(C)SUBSETREG/REF in second_NegNot_assign
* changed the way OP_NEG and OP_NOT are handled in op_reg_ref, in order to be
  consistent with op_reg_reg
* introduced op_reg,op_ref,op_subsetreg,op_subsetref and op_loc for the unary
  operations only (OP_NEG,OP_NOT)

git-svn-id: trunk@45302 -
(cherry picked from commit 0f6ab0de17)

# Conflicts:
#	compiler/cgobj.pas
2021-10-24 12:40:38 +02:00
florian
d75fb82753 * do not reuse a loaded reference for avrtiny in a_op_const*, resolves #38142
git-svn-id: trunk@47612 -
(cherry picked from commit eb098a3d11)

# Conflicts:
#	compiler/cgobj.pas
2021-10-24 12:40:38 +02:00
Jonas Maebe
76045bfc04 * merged macOS/AArch64 support + revisions these changes depended on
git-svn-id: branches/fixes_3_2@46866 -
2020-09-15 19:40:36 +00:00
pierre
d1f31fab15 Merge commits 42525 and 45891 that add
checks for fpu exceptions for arm and aarch64.
------------------------------------------------------------------------
r42525 | florian | 2019-07-28 21:06:36 +0000 (Sun, 28 Jul 2019) | 2 lines

+ software handling of exceptions on arm
* reworked software handling of exceptions so they can be check lazily
------------------------------------------------------------------------
--- Merging r42525 into '.':
U    compiler/arm/cgcpu.pas
U    compiler/arm/narmadd.pas
U    compiler/arm/narminl.pas
U    compiler/arm/narmmat.pas
U    compiler/ncgcal.pas
U    compiler/procinfo.pas
U    rtl/arm/arm.inc
--- Recording mergeinfo for merge of r42525 into '.':
 U   .
Summary of conflicts:
  Tree conflicts: 1
------------------------------------------------------------------------
r42891 | florian | 2019-09-01 17:26:11 +0000 (Sun, 01 Sep 2019) | 1 line

+ support for software floating point exception handling on AArch64 (-CE)
------------------------------------------------------------------------
--- Merging r42891 into '.':
U    compiler/aarch64/cgcpu.pas
U    compiler/aarch64/ncpuadd.pas
U    compiler/aarch64/ncpuinl.pas
U    compiler/aarch64/ncpumat.pas
U    rtl/aarch64/aarch64.inc
U    rtl/aarch64/math.inc
U    rtl/aarch64/mathu.inc
--- Recording mergeinfo for merge of r42891 into '.':
 G   .

git-svn-id: branches/fixes_3_2@46225 -
2020-08-04 10:30:50 +00:00
Jonas Maebe
846da37c9f --- Merging r41243 into '.':
U    rtl/inc/objc.pp
--- Recording mergeinfo for merge of r41243 into '.':
 U   .
--- Merging r41335 into '.':
U    compiler/arm/cgcpu.pas
U    compiler/cgobj.pas
--- Recording mergeinfo for merge of r41335 into '.':
 G   .
--- Merging r41422 into '.':
U    compiler/scanner.pas
--- Recording mergeinfo for merge of r41422 into '.':
 G   .
--- Merging r41474 into '.':
U    compiler/pexpr.pas
A    tests/webtbf/tw35149a.pp
A    tests/webtbs/tw35149.pp
--- Recording mergeinfo for merge of r41474 into '.':
 G   .
--- Merging r41650 into '.':
U    compiler/aarch64/racpugas.pas
--- Recording mergeinfo for merge of r41650 into '.':
 G   .
--- Merging r41651 into '.':
U    tests/test/taarch64abi.pp
--- Recording mergeinfo for merge of r41651 into '.':
 G   .
--- Merging r41905 into '.':
U    compiler/utils/ppuutils/ppudump.pp
--- Recording mergeinfo for merge of r41905 into '.':
 G   .

git-svn-id: branches/fixes_3_2@41943 -
2019-04-27 19:21:30 +00:00
Jonas Maebe
d69ad8fa41 * removed temppos field again from parameter locations: they're not allocated
by the temp manager of the current procedure

git-svn-id: trunk@38858 -
2018-04-27 19:18:55 +00:00
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references,
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
2018-04-22 17:03:16 +00:00
nickysn
518cdf9674 * replaced the saved_XXX_registers arrays with virtual methods inside
tcpuparamanager, very similar to the existing get_volatile_registers_XXX. The
  new methods are called get_saved_registers_XXX, where XXX is the register
  type ("int", "address", "fpu" or "mm")

git-svn-id: trunk@38794 -
2018-04-19 21:22:16 +00:00
florian
f08d3fdf8f * moved execution weight calculation into a separate pass, so the info is available already available before the code generation pass if needed
git-svn-id: trunk@38717 -
2018-04-08 20:51:27 +00:00
florian
d86ffb9bfb + tcg.a_op_loc_reg
+ optimized tx86addnode.second_ordinal for x86

git-svn-id: trunk@38500 -
2018-03-11 16:32:26 +00:00
pierre
c63981e5b5 Fix msdos failure due to copy/paste error in previous commit
git-svn-id: trunk@37611 -
2017-11-20 21:45:29 +00:00
florian
010a6f5016 + shift by 8 and 16 on 8 and 16 bit cpus by simple register moves
git-svn-id: trunk@37606 -
2017-11-19 18:05:18 +00:00
florian
f0c237a159 + let a_load_loc_reg handle also LOC_*MMREGISTER as we have loadmm_*intreg*
git-svn-id: trunk@37372 -
2017-10-01 16:13:18 +00:00
florian
9ef646e3c5 * fix avr for new GetNextReg behaviour
* some wrong GetNextReg usage in the avr code generator fixed

git-svn-id: trunk@37316 -
2017-09-24 20:51:05 +00:00
nickysn
c8b351fb67 + added check in GetNextReg(), so it halts with an internal error, if called on
a register, that isn't supposed to have a "next" register allocated

git-svn-id: trunk@37185 -
2017-09-11 18:23:14 +00:00
nickysn
db09759763 * also integrated the getnextreg() implementation for 8-bit and 16-bit alus from
the avr and i8086 code generators into the base tcg class

git-svn-id: trunk@37182 -
2017-09-11 15:47:39 +00:00
nickysn
cf28b202eb * integrated the getintregister() implementation for 8-bit and 16-bit alus from
the avr and i8086 code generators into the base tcg class (so it can be reused
  by other 8-bit and 16-bit targets)

git-svn-id: trunk@37181 -
2017-09-11 15:23:59 +00:00
nickysn
ddba821561 * GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved
from cpubase unit to a method in the tcg class. The reason for doing that is
  that this is now a standard part of the 16-bit and 8-bit code generators and
  moving to the tcg class allows doing extra checks (not done yet, but for
  example, in the future, we can keep track of whether there was an extra
  register allocated with getintregister and halt with an internalerror in case
  GetNextReg() is called for registers, which weren't allocated as a part of a
  sequence, therefore catching a certain class of 8-bit and 16-bit code
  generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
  anything. It might be added to the tcg class, in case it's ever needed, but
  for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.

git-svn-id: trunk@37180 -
2017-09-11 14:53:06 +00:00
florian
4d5a94644f * do not call a_load_reg_reg with tosize=OS_NO
git-svn-id: trunk@37055 -
2017-08-24 20:09:15 +00:00
florian
99ce914a61 * fix tcg.a_load_cgparaloc_ref for ref. sizes of 7 on little endian systems
git-svn-id: trunk@37002 -
2017-08-21 09:08:02 +00:00
florian
4a54a88cca + implement tcg.a_load_cgparaloc_ref for un-even sizes and little endian systems as well
git-svn-id: trunk@36977 -
2017-08-20 18:40:58 +00:00
florian
43b017bde0 * tcg.a_load_cgparaloc_ref checks the size of the ref exactly to avoid overwriting of adjacent data
git-svn-id: trunk@36951 -
2017-08-20 15:21:59 +00:00
florian
bccc2f6863 + tcg.a_loadfpu_intreg_reg, make use of it in tcg.a_load_cgparaloc_anyreg
git-svn-id: trunk@36717 -
2017-07-09 21:33:24 +00:00
florian
b1dff29cbf * removed unused units
git-svn-id: trunk@36165 -
2017-05-09 19:53:14 +00:00
nickysn
e79f49a2b4 + mask only the low bits that matter for the const of OP_ROL and OP_ROR in
tcg.optimize_op_const()

git-svn-id: trunk@36036 -
2017-05-01 14:18:37 +00:00
nickysn
9a1812dfd9 + optimize OP_XOR by 0 to OP_NONE in optimize_op_const
git-svn-id: trunk@35936 -
2017-04-24 14:26:33 +00:00
nickysn
9187825e3a * fixed tnegnotassign1.pp on powerpc and other RISC cpus
git-svn-id: trunk@35757 -
2017-04-09 14:28:13 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
2016-11-27 18:17:37 +00:00
Jonas Maebe
aa1be3276f - removed default value of _typ parameter of TAsmData.(Weak)RefAsmSymbol():
it was AT_NONE, which is invalid and should never be used
  * explicitly pass the correct value for all calls to those methods elsewhere
    in the compiler

git-svn-id: trunk@34250 -
2016-08-05 07:09:16 +00:00
Jonas Maebe
1cb8c0d00c * specify the def of assembler level symbols defined via
tasmdata.DefineAsmSymbol() and all routines that call it
   o will be used to automatically generate AB_INDIRECT sybols when
     necessary

git-svn-id: trunk@34164 -
2016-07-20 20:52:59 +00:00
Jonas Maebe
a5dba44fd3 * fixed sign extension for unaligned loads (mantis #29891, although that
code shouldn't use unaligned loads in the first place)

git-svn-id: trunk@33382 -
2016-03-29 14:52:27 +00:00
Jonas Maebe
1320d6bdba * correctly handle negative paraloc shift values for non power-of-2 sized
paralocs (e.g. a 3 byte record) in case the data's size has been
    rounded up to the next power of two as far as the paraloc is concerned
    (because those 3 bytes had to be shifted to be located in the upper 3
     bytes of a 4 byte location)

git-svn-id: trunk@32633 -
2015-12-10 22:45:56 +00:00
Jonas Maebe
3f736f6114 * handle the loading of VMT entries at the node level, so it's done in a
type-safe way (for LLVM, and also internal consistency checking between
    the VMT as generated in nobj.pas and ncgvmt.pas)
   o also converted the VMT validity checking to the node level

git-svn-id: trunk@30950 -
2015-05-31 16:50:47 +00:00
florian
d598351664 * call also optimize_op_const in the generic a_op_const_reg_reg
git-svn-id: trunk@30658 -
2015-04-19 10:04:57 +00:00
Jonas Maebe
61e4a1b811 + added tasmlist parameter to getintparaloc() (needed for llvm)
git-svn-id: trunk@30429 -
2015-04-04 14:29:16 +00:00
Jonas Maebe
bd203a5b57 * synchronised with trunk till r30240
git-svn-id: branches/hlcgllvm@30241 -
2015-03-15 19:44:58 +00:00
Jonas Maebe
622852b8c9 * check that a_load_cgparaloc_anyreg() is not used to try to move an fpu
register into a non-fpu register, as this is not (yet) supported

git-svn-id: trunk@30226 -
2015-03-14 18:36:54 +00:00
Jonas Maebe
6d02aedf70 * support multiple register paralocs in tcgobj.a_loadfpu_ref_cgpara()
git-svn-id: trunk@30223 -
2015-03-14 18:36:46 +00:00
Jonas Maebe
67b8aceaee * synchronized with privatetrunk till r30095
git-svn-id: branches/hlcgllvm@30101 -
2015-03-05 20:32:15 +00:00
Jonas Maebe
2ab7f5c35d * moved x86-specific requirements from the generic bsr/bsf code to the
x86 code generator (register size constraints)

git-svn-id: trunk@29984 -
2015-02-23 22:57:18 +00:00
Jonas Maebe
504a9d1594 * fixed register sizes in a_load_ref_reg_unaligned()
git-svn-id: trunk@29821 -
2015-02-23 22:47:50 +00:00
Jonas Maebe
e6511bcb33 * support multiple paralocs in a_load_reg_cgpara() by taking a round trip
via a_load_ref_cgpara()

git-svn-id: trunk@29814 -
2015-02-23 22:47:29 +00:00
sergei
8f4430e795 * tcg.translate_register: check that reg.allocator is not nil before calling its method (in case of "assembler nostackframe" function returning an x87 float compiler tries to translate NR_ST which is used for function result).
* tcg.a_reg_dealloc: ignore NR_NO, prevents creating useless deallocations of NR_DEFAULTFLAGS on MIPS targets which have NR_DEFAULTFLAGS=NR_NO.

git-svn-id: trunk@29242 -
2014-12-10 07:13:14 +00:00
Jonas Maebe
b745dcc64c * moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because
for some platforms it depends on that routine

git-svn-id: branches/hlcgllvm@28492 -
2014-08-19 20:22:54 +00:00
Jonas Maebe
a637fbe596 * moved all g_exception_*() methods to hlcgobj and cleaned them up (no more
hardcoded registers for the most part)
  + added extra g_exception_discard_reason() that can be called when we only
    want to get rid of the currently pushed exception reason, and don't have
    to load it (so it can do nothing on platforms that don't use push/pop)

git-svn-id: branches/hlcgllvm@28481 -
2014-08-19 20:22:24 +00:00
Jonas Maebe
5c75b6dd6b * synchronised with trunk up till r28402
git-svn-id: branches/hlcgllvm@28403 -
2014-08-13 16:04:30 +00:00