J. Gareth "Curious Kit" Moreton
6f24c8b4ef
* x86: Code generation fixes where FLAGS
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register is not properly allocated.
2022-04-27 20:46:32 +00:00
florian
637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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git-svn-id: trunk@47103 -
2020-10-13 19:59:01 +00:00
florian
8c5606b41d
+ support mmx shifting
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git-svn-id: trunk@38367 -
2018-02-27 21:40:12 +00:00
nickysn
aa415bfc6b
+ optimized division by negative power of 2 constants in the i8086 code
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generator as well
git-svn-id: trunk@37004 -
2017-08-21 11:56:11 +00:00
nickysn
b92b0eac83
* also improve the code, generated for signed division by 2 on i8086, when
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optimize cpu target is 486+, by replacing the sequence
sar reg, 15
and reg, 1
with:
shr reg, 15
git-svn-id: trunk@36807 -
2017-07-28 15:38:40 +00:00
nickysn
bb7cd4866d
* corrected comment in x86 division code - it said "signed", when it actually meant "negative"
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git-svn-id: trunk@36799 -
2017-07-27 15:04:56 +00:00
nickysn
b8c4dd9e18
+ implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and
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use it in the shl/shr node for code generation.
git-svn-id: trunk@36018 -
2017-04-29 21:57:48 +00:00
nickysn
a82c89d894
+ implemented OP_SHR,OP_SHL and OP_SAR in a_op64_const_reg for i8086. The shlshr
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node now uses them for 64-bit shift by constant.
git-svn-id: trunk@36017 -
2017-04-29 20:58:55 +00:00
nickysn
b957b65ec8
* generate better i8086 code for 64-bit shl/shr, by masking the shift count by 63
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git-svn-id: trunk@35730 -
2017-04-04 17:58:00 +00:00
nickysn
7e6ba9db2a
* do an even better optimization (swap registers in the result, saving 2 mov
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instructions) on i8086 for 64-bit shl/shr with a constant in the range 32..47
git-svn-id: trunk@32062 -
2015-10-15 21:13:28 +00:00
nickysn
ff5eed1c00
* user xor reg,reg to zero out registers in the i8086 optimized 64-bit shl code
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git-svn-id: trunk@32061 -
2015-10-15 21:02:53 +00:00
nickysn
6ece867305
* in the i8086 64-bit shl code, use jcxz instead of test cx,cx+jz when
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optimization target is 386 or earlier (or when optimizing for size)
git-svn-id: trunk@32060 -
2015-10-15 20:51:20 +00:00
nickysn
dc92c3eb09
+ i8086 optimization for the code generated for 64-bit shl/shr with a constant in the range 32..47
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git-svn-id: trunk@32059 -
2015-10-15 15:59:27 +00:00
nickysn
44f6f607c5
* optimized the generated code on i8086 for 64-bit shl/shr with constant >=48
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git-svn-id: trunk@32058 -
2015-10-15 15:15:11 +00:00
Károly Balogh
dd67fa8c5c
* fixed DFA warnings for i8086
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git-svn-id: trunk@28504 -
2014-08-20 15:49:27 +00:00
nickysn
dc432918da
+ enabled the use of the DIV/IDIV instruction for 16-bit div/mod on i8086
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* ti8086.moddivnode.pass_generate_code: use cg.a_op_const_reg, instead of
emit_const_reg, in order to support generating plain 8086/8088 code
(shr/shl/sar reg,const is 186+ if const is >= 2).
git-svn-id: trunk@26063 -
2013-11-11 22:34:41 +00:00
nickysn
bd083c0b8e
* ti8086moddivnode.pass_generate_code converted to 16-bit. Note that this code
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is still not active, due to the cpuneedsdiv32helper define, but will
eventually be enabled for 16-bit divisions.
git-svn-id: trunk@26062 -
2013-11-11 21:01:13 +00:00
nickysn
43dba74a5c
+ implemented 64-bit shl and shr for i8086
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git-svn-id: branches/i8086@23882 -
2013-03-17 02:11:25 +00:00
nickysn
19cbff220e
+ added unit n8086mat, based on n386mat; TODO: adapt to i8086
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git-svn-id: branches/i8086@23805 -
2013-03-12 14:30:26 +00:00
