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30 Commits

Author SHA1 Message Date
florian
4eb8f8e565 * patch by Marģers 
- Rename 3DNow instruction (fixed long lasting typo in mnemonic). PMULHRWA  --> PMULHRW
    - Add vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq, vpclmulhqhqdq.
    - Fix "typo" for SHA1MSG2
 2024-05-30 21:49:30 +02:00
florian
6c7e6191f6 + support of SHA extension in the internal assembler 2021-10-09 15:44:46 +02:00
florian
963fe73d19 + support all XSAVE instructions, resolves #37864 
git-svn-id: trunk@47042 -
 2020-10-03 14:51:31 +00:00
tg74
1454e8b29d new avx512-opcodes VBMI2,VNNI,BITALG ... 
git-svn-id: branches/tg74/avx512merge@43406 -
 2019-11-06 19:51:01 +00:00
florian
746bfced25 Synchronized with trunk, part 1 (only make cycle tested, make all is broken, avx-512 support not yet tested 
git-svn-id: branches/tg74/avx512@42642 -
 2019-08-10 13:53:20 +00:00
florian
4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 
+ avxopcodes tests also movbe and pclmulqdq

git-svn-id: trunk@40951 -
 2019-01-20 18:50:12 +00:00
florian
8943c0584e + patch by J. Gareth Moreton to support BMI2 instructions 
+ extended avx test generator with the newly added BMI2 instructions

git-svn-id: trunk@39875 -
 2018-10-07 10:10:19 +00:00
tg74
dd967ecfee remove any gather/scatter opcodes for nights mill 
git-svn-id: branches/tg74/avx512@39742 -
 2018-09-12 09:59:04 +00:00
tg74
c611e4814a new avx512 opcodes 
git-svn-id: branches/tg74/avx512@39720 -
 2018-09-10 06:19:45 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes 
git-svn-id: branches/tg74/avx512@39705 -
 2018-09-03 05:40:44 +00:00
tg74
914e31dbd1 new AVX512 instructions vextracti..,vextractf.. 
git-svn-id: branches/tg74/avx512@39674 -
 2018-08-27 06:06:27 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512 
git-svn-id: branches/tg74/avx512@39636 -
 2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register 
git-svn-id: branches/tg74/avx512@39457 -
 2018-07-16 17:06:57 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd. 
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
 2018-03-03 23:32:54 +00:00
marco
f21a141144 * mantis #32001, add 32 vcmpps variants. 
git-svn-id: trunk@38403 -
 2018-03-03 23:10:03 +00:00
nickysn
ae92973196 + added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and 
retfq x86 instructions. These are variants of the ret instruction with the
  return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
  a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
  32-bit offset, followed by a 16-bit segment), etc.

git-svn-id: trunk@37571 -
 2017-11-10 16:53:29 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions 
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
 2017-10-12 00:07:02 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933 
git-svn-id: trunk@34917 -
 2016-11-18 20:19:39 +00:00
florian
406e3c4ac1 + support xgetbv instruction, resolves issue #29958 
git-svn-id: trunk@33418 -
 2016-04-03 20:53:10 +00:00
florian
8d5cc3dfa4 * (extended and modified) patch by Emelyanov Roman to add suport of RDRAND, RDSEED and TSX instructions set, resolves issue #29893. 
In comparison with the original patch, support for a i386 has been added as well as a test program. 
  Further, a small issue with xbegin has been fixed

git-svn-id: trunk@33375 -
 2016-03-28 19:08:13 +00:00
florian
a3964d9ee0 + support for RDTSCP, resolves issue #28916 
git-svn-id: trunk@32652 -
 2015-12-13 13:28:51 +00:00
florian
d6e4af8279 + applied remaining patches of Torsten Grundke: adds gather instructions of avx2 
git-svn-id: trunk@29745 -
 2015-02-17 21:43:46 +00:00
sergei
dc628b8969 * x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway. 
git-svn-id: trunk@27934 -
 2014-06-11 22:31:40 +00:00
florian
842e027a9f + prove of concept how FMA4 could be supported in inline assembler 
git-svn-id: trunk@27214 -
 2014-03-20 21:25:38 +00:00
florian
a79be2b05c + support for FMA instructions in inline assembler 
+ extended avx test code with FMA

git-svn-id: trunk@27209 -
 2014-03-20 20:06:56 +00:00
florian
aa107b914c * merged avx2 branch, developed by Torsten Grundke 
git-svn-id: trunk@27200 -
 2014-03-20 12:03:52 +00:00
florian
7028210817 + tzcnt assembler instruction 
git-svn-id: trunk@26506 -
 2014-01-18 12:11:50 +00:00
nickysn
f6e846c574 + added the NEC V20/V30 instructions 
git-svn-id: trunk@25750 -
 2013-10-11 21:27:56 +00:00
nickysn
4929bc5694 * regenerated the i8086 ins files 
git-svn-id: trunk@25603 -
 2013-09-28 21:10:23 +00:00
nickysn
107a6f6552 * i8086 versions of i386*.inc and r386*.inc renamed to i8086*.inc and r8086*.inc 
git-svn-id: branches/i8086@24232 -
 2013-04-12 12:06:28 +00:00